#ifndef __SN32F770_SYS_CON_H
#define __SN32F770_SYS_CON_H

/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F770.h>
#include <SN32F700_Def.h>


/*_____ D E F I N I T I O N S ______________________________________________*/

//Clock
#define	SYS0_CLK_IHRC12					0
#define	SYS0_CLK_IHRC24					1
#define	SYS0_CLK_IHRC48					2
#define	SYS0_CLK_ILRC					  3


//<---------------- SYS0_ANBCTRL ---------------->
//IHRC Enable/Disable
#define	SYS0_IHRC_DISABLE				0
#define	SYS0_IHRC_12MHZ					1
#define	SYS0_IHRC_24MHZ					2
#define	SYS0_IHRC_48MHZ					4


//<---------------- SYS0_CSST ---------------->
//Clock Source Ready Status (R)
#define	SYS0_IHRC_READY					1
#define	SYS0_IHRC_NOT_READY			0
#define	mskSYS0_IHRC_READY			SYS0_IHRC_READY


//<---------------- SYS0_CLKCFG ---------------->
//System Clock Selection
#define	SYS0_SYSCLK_IHRC				0
#define	SYS0_SYSCLK_ILRC				1
#define	mskSYS0_SYSCLK_IHRC			SYS0_SYSCLK_IHRC
#define	mskSYS0_SYSCLK_ILRC			SYS0_SYSCLK_ILRC

//System Clock Switch Status (R)
#define	SYS0_SYSCLK_SW_IHRC			0
#define	SYS0_SYSCLK_SW_ILRC			1
#define	mskSYS0_SYSCLK_SW_IHRC	(SYS0_SYSCLK_SW_IHRC<<4)
#define	mskSYS0_SYSCLK_SW_ILRC	(SYS0_SYSCLK_SW_ILRC<<4)

//<---------------- SYS0_AHBCP ---------------->
#define	SYS0_AHBPRE_DIV1				0
#define	SYS0_AHBPRE_DIV2				1
#define	SYS0_AHBPRE_DIV4				2
#define	SYS0_AHBPRE_DIV8				3
#define	SYS0_AHBPRE_DIV16				4
#define	SYS0_AHBPRE_DIV32				5
#define	SYS0_AHBPRE_DIV64				6
#define	SYS0_AHBPRE_DIV128			7

//<---------------- SYS0_RSTST ---------------->
//System Reset Status
#define	mskSYS0_SW_RESET				0x1
#define	mskSYS0_WDT_RESET				0x2
#define	mskSYS0_LVD_RESET				0x4
#define	mskSYS0_EXT_RESET				0x8
#define	mskSYS0_POR_RESET				0x10

//<---------------- SYS0_LVDCTRL ---------------->
//LVD
#define	SYS0_LVD_ENABLE								1
#define	SYS0_LVD_DISABLE							0
#define	mskSYS0_LVD_ENABLE						(SYS0_LVD_ENABLE<<15)
#define	mskSYS0_LVD_DISABLE						(SYS0_LVD_DISABLE<<15)

#define	SYS0_LVD_RESET_ENABLE					1
#define	SYS0_LVD_RESET_DISABLE				0
#define	mskSYS0_LVD_RESET_ENABLE			(SYS0_LVD_RESET_ENABLE<<14)
#define	mskSYS0_LVD_RESET_DISABLE			(SYS0_LVD_RESET_DISABLE<<14)

#define	SYS0_LVD_INT_2P7V							3
#define	SYS0_LVD_INT_3P0V							4
#define	SYS0_LVD_INT_3P6V							5
#define	mskSYS0_LVD_INT_2P7V					(SYS0_LVD_INT_2P7V<<4)
#define	mskSYS0_LVD_INT_3P0V					(SYS0_LVD_INT_3P0V<<4)
#define	mskSYS0_LVD_INT_3P6V					(SYS0_LVD_INT_3P6V<<4)

#define	SYS0_LVD_RESET_2P7V						3
#define	SYS0_LVD_RESET_3P0V						4
#define	SYS0_LVD_RESET_3P6V						5
#define	mskSYS0_LVD_RESET_2P7V				SYS0_LVD_RESET_2P7V
#define	mskSYS0_LVD_RESET_3P0V				SYS0_LVD_RESET_3P0V
#define	mskSYS0_LVD_RESET_3P6V				SYS0_LVD_RESET_3P6V


//<---------------- SYS1_AHBCLKEN ---------------->
//Clockout
#define	SYS1_CLOCKOUT_DISABLE					0
#define	SYS1_CLOCKOUT_ILRC						1
#define	SYS1_CLOCKOUT_HCLK						4
#define	SYS1_CLOCKOUT_IHRC						5

#define	mskSYS1_CLOCKOUT_DISABLE			(SYS1_CLOCKOUT_DISABLE<<28)
#define	mskSYS1_CLOCKOUT_ILRC					(SYS1_CLOCKOUT_ILRC<<28)
#define	mskSYS1_CLOCKOUT_HCLK					(SYS1_CLOCKOUT_HCLK<<28)
#define	mskSYS1_CLOCKOUT_IHRC					(SYS1_CLOCKOUT_IHRC<<28)


//<---------------- SYS1_APBCP1 ---------------->
#define	SYS1_CLOCKOUT_DIV1						0
#define	SYS1_CLOCKOUT_DIV2						1
#define	SYS1_CLOCKOUT_DIV4						2
#define	SYS1_CLOCKOUT_DIV8						3
#define	SYS1_CLOCKOUT_DIV16						4
#define	SYS1_CLOCKOUT_DIV32						5
#define	SYS1_CLOCKOUT_DIV64						6
#define	SYS1_CLOCKOUT_DIV128					7


/*_____ M A C R O S ________________________________________________________*/

//Clock Enable/Disable
#define	__SYS0_IHRC12_ENABLE							SN_SYS0->ANBCTRL_b.IHRCEN = SYS0_IHRC_12MHZ
#define	__SYS0_IHRC24_ENABLE							SN_SYS0->ANBCTRL_b.IHRCEN = SYS0_IHRC_24MHZ
#define	__SYS0_IHRC48_ENABLE							SN_SYS0->ANBCTRL_b.IHRCEN = SYS0_IHRC_48MHZ
#define	__SYS0_IHRC_DISABLE								SN_SYS0->ANBCTRL_b.IHRCEN = SYS0_IHRC_DISABLE


//Clock Source Ready Status (R)
#define	__SYS0_CHECK_IHRC_READY_STATUS		(SN_SYS0->CSST & mskSYS0_IHRC_READY)


//System Clock (HCLK) Switch Status (R)
#define	__SYS0_CHECK_SYSCLK_SW_STATUS			(SN_SYS0->CLKCFG & 0x70)

//Clear System Reset Status
#define	__SYS0_CLEAR_SW_RESET							SN_SYS0->RSTST_b.SWRSTF = 0
#define	__SYS0_CLEAR_WDT_RESET						SN_SYS0->RSTST_b.WDTRSTF = 0
#define	__SYS0_CLEAR_LVD_RESET						SN_SYS0->RSTST_b.LVDRSTF = 0
#define	__SYS0_CLEAR_EXT_RESET						SN_SYS0->RSTST_b.EXTRSTF = 0
#define	__SYS0_CLEAR_POR_RESET						SN_SYS0->RSTST_b.PORRSTF = 0

//External Reset pin Enable/Disable
#define	__SYS0_EXT_RESET_ENABLE						SN_SYS0->EXRSTCTRL = 0
#define	__SYS0_EXT_RESET_DISABLE					SN_SYS0->EXRSTCTRL = 1

//SWD pin Enable/Disable
#define	__SYS0_SWD_ENABLE									SN_SYS0->SWDCTRL = 0
#define	__SYS0_SWD_DISABLE								SN_SYS0->SWDCTRL = 1


/*_____ D E C L A R A T I O N S ____________________________________________*/

//Reset status
uint32_t SYS0_GetResetStatus(uint32_t mskRst);

//Clock Switch
void SYS0_EnableIHRC(uint32_t);
void SYS0_SystemClockSwitch(uint32_t, uint32_t);
void SYS0_SystemCoreClockUpdate(uint32_t hclk);
void SYS1_EnableClockout(uint32_t src, uint32_t prescale);

//LVD
void SYS0_LvdControl(uint32_t LvdEn, uint32_t IntLvl, uint32_t RstEn, uint32_t RstLvl);

#endif	/*__SN32F770_SYS_CON_H*/
