#ifndef __SN32F780_CMP_H
#define __SN32F780_CMP_H

/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F780.h>
#include <SN32F700_Def.h>

/*_____ D E F I N I T I O N S ______________________________________________*/
//CM0PS, CM1PS, CM2PS
#define	CMP_VPREF_RESERVED				0
#define	CMP_VPREF_CMnP0						1
#define	CMP_VPREF_CMnP1						2
#define	CMP_VPREF_CMnP2						3

#define	mskCMP_CM0PREF_RESERVED		(CMP_VPREF_RESERVED << 1)
#define	mskCMP_CM0PREF_CM0P0			(CMP_VPREF_CMnP0 << 1)
#define	mskCMP_CM0PREF_CM0P1			(CMP_VPREF_CMnP1 << 1)
#define	mskCMP_CM0PREF_CM0P2			(CMP_VPREF_CMnP2 << 1)

#define	mskCMP_CM1PREF_RESERVED		(CMP_VPREF_RESERVED << 17)
#define	mskCMP_CM1PREF_CM1P0			(CMP_VPREF_CMnP0 << 17)
#define	mskCMP_CM1PREF_CM1P1			(CMP_VPREF_CMnP1 << 17)
#define	mskCMP_CM1PREF_CM1P2			(CMP_VPREF_CMnP2 << 17)

#define	mskCMP_CM2PREF_RESERVED		(CMP_VPREF_RESERVED << 1)
#define	mskCMP_CM2PREF_CM2P0			(CMP_VPREF_CMnP0 << 1)
#define	mskCMP_CM2PREF_CM2P1			(CMP_VPREF_CMnP1 << 1)
#define	mskCMP_CM2PREF_CM2P2			(CMP_VPREF_CMnP2 << 1)

//CM0NS, CM1NS, CM2NS
#define	CMP_VNREF_CMnN0						0
#define	CMP_VNREF_CMnN1						1
#define	CMP_VNREF_CMnN2						2
#define	CMP_VNREF_VIREFn					3

#define	mskCMP_CM0NS_CM0N0				(CMP_VNREF_CMnN0 << 3)
#define	mskCMP_CM0NS_CM0N1				(CMP_VNREF_CMnN1 << 3)
#define	mskCMP_CM0NS_CM0N2				(CMP_VNREF_CMnN2 << 3)
#define	mskCMP_CM0NREF_VIREF0			(CMP_VNREF_VIREFn << 3)

#define	mskCMP_CM1NS_CM1N0				(CMP_VNREF_CMnN0 << 19)
#define	mskCMP_CM1NS_CM1N1				(CMP_VNREF_CMnN1 << 19)
#define	mskCMP_CM1NS_CM1N2				(CMP_VNREF_CMnN2 << 19)
#define	mskCMP_CM1NREF_VIREF1			(CMP_VNREF_VIREFn <<19)

#define	mskCMP_CM2NS_CM2N0				(CMP_VNREF_CMnN0 << 3)
#define	mskCMP_CM2NS_CM2N1				(CMP_VNREF_CMnN1 << 3)
#define	mskCMP_CM2NS_CM2N2				(CMP_VNREF_CMnN2 << 3)
#define	mskCMP_CM2NREF_VIREF2			(CMP_VNREF_VIREFn << 3)

//CM0RS
#define	mskCMP_CM0RS_VIREF				(0 << 5)
#define	mskCMP_CM0RS_VIREF_M01D32	(1 << 5)
#define	mskCMP_CM0RS_VIREF_M02D32	(2 << 5)
#define	mskCMP_CM0RS_VIREF_M03D32	(3 << 5)
#define	mskCMP_CM0RS_VIREF_M04D32	(4 << 5)
#define	mskCMP_CM0RS_VIREF_M05D32	(5 << 5)
#define	mskCMP_CM0RS_VIREF_M06D32	(6 << 5)
#define	mskCMP_CM0RS_VIREF_M07D32	(7 << 5)
#define	mskCMP_CM0RS_VIREF_M08D32	(8 << 5)
#define	mskCMP_CM0RS_VIREF_M09D32	(9 << 5)
#define	mskCMP_CM0RS_VIREF_M10D32	(10 << 5)
#define	mskCMP_CM0RS_VIREF_M11D32	(11 << 5)
#define	mskCMP_CM0RS_VIREF_M12D32	(12 << 5)
#define	mskCMP_CM0RS_VIREF_M13D32	(13 << 5)
#define	mskCMP_CM0RS_VIREF_M14D32	(14 << 5)
#define	mskCMP_CM0RS_VIREF_M15D32	(15 << 5)
#define	mskCMP_CM0RS_VIREF_M16D32	(16 << 5)
#define	mskCMP_CM0RS_VIREF_M17D32	(17 << 5)
#define	mskCMP_CM0RS_VIREF_M18D32	(18 << 5)
#define	mskCMP_CM0RS_VIREF_M19D32	(19 << 5)
#define	mskCMP_CM0RS_VIREF_M20D32	(20 << 5)
#define	mskCMP_CM0RS_VIREF_M21D32	(21 << 5)
#define	mskCMP_CM0RS_VIREF_M22D32	(22 << 5)
#define	mskCMP_CM0RS_VIREF_M23D32	(23 << 5)
#define	mskCMP_CM0RS_VIREF_M24D32	(24 << 5)
#define	mskCMP_CM0RS_VIREF_M25D32	(25 << 5)
#define	mskCMP_CM0RS_VIREF_M26D32	(26 << 5)
#define	mskCMP_CM0RS_VIREF_M27D32	(27 << 5)
#define	mskCMP_CM0RS_VIREF_M28D32	(28 << 5)
#define	mskCMP_CM0RS_VIREF_M29D32	(29 << 5)
#define	mskCMP_CM0RS_VIREF_M30D32	(30 << 5)
#define	mskCMP_CM0RS_VIREF_M31D32	(31 << 5)

//CM1RS
#define	mskCMP_CM1RS_VIREF				(0 << 21)
#define	mskCMP_CM1RS_VIREF_M01D32	(1 << 21)
#define	mskCMP_CM1RS_VIREF_M02D32	(2 << 21)
#define	mskCMP_CM1RS_VIREF_M03D32	(3 << 21)
#define	mskCMP_CM1RS_VIREF_M04D32	(4 << 21)
#define	mskCMP_CM1RS_VIREF_M05D32	(5 << 21)
#define	mskCMP_CM1RS_VIREF_M06D32	(6 << 21)
#define	mskCMP_CM1RS_VIREF_M07D32	(7 << 21)
#define	mskCMP_CM1RS_VIREF_M08D32	(8 << 21)
#define	mskCMP_CM1RS_VIREF_M09D32	(9 << 21)
#define	mskCMP_CM1RS_VIREF_M10D32	(10 << 21)
#define	mskCMP_CM1RS_VIREF_M11D32	(11 << 21)
#define	mskCMP_CM1RS_VIREF_M12D32	(12 << 21)
#define	mskCMP_CM1RS_VIREF_M13D32	(13 << 21)
#define	mskCMP_CM1RS_VIREF_M14D32	(14 << 21)
#define	mskCMP_CM1RS_VIREF_M15D32	(15 << 21)
#define	mskCMP_CM1RS_VIREF_M16D32	(16 << 21)
#define	mskCMP_CM1RS_VIREF_M17D32	(17 << 21)
#define	mskCMP_CM1RS_VIREF_M18D32	(18 << 21)
#define	mskCMP_CM1RS_VIREF_M19D32	(19 << 21)
#define	mskCMP_CM1RS_VIREF_M20D32	(20 << 21)
#define	mskCMP_CM1RS_VIREF_M21D32	(21 << 21)
#define	mskCMP_CM1RS_VIREF_M22D32	(22 << 21)
#define	mskCMP_CM1RS_VIREF_M23D32	(23 << 21)
#define	mskCMP_CM1RS_VIREF_M24D32	(24 << 21)
#define	mskCMP_CM1RS_VIREF_M25D32	(25 << 21)
#define	mskCMP_CM1RS_VIREF_M26D32	(26 << 21)
#define	mskCMP_CM1RS_VIREF_M27D32	(27 << 21)
#define	mskCMP_CM1RS_VIREF_M28D32	(28 << 21)
#define	mskCMP_CM1RS_VIREF_M29D32	(29 << 21)
#define	mskCMP_CM1RS_VIREF_M30D32	(30 << 21)
#define	mskCMP_CM1RS_VIREF_M31D32	(31 << 21)

//CM2RS
#define	mskCMP_CM2RS_VIREF				(0 << 5)
#define	mskCMP_CM2RS_VIREF_M01D32	(1 << 5)
#define	mskCMP_CM2RS_VIREF_M02D32	(2 << 5)
#define	mskCMP_CM2RS_VIREF_M03D32	(3 << 5)
#define	mskCMP_CM2RS_VIREF_M04D32	(4 << 5)
#define	mskCMP_CM2RS_VIREF_M05D32	(5 << 5)
#define	mskCMP_CM2RS_VIREF_M06D32	(6 << 5)
#define	mskCMP_CM2RS_VIREF_M07D32	(7 << 5)
#define	mskCMP_CM2RS_VIREF_M08D32	(8 << 5)
#define	mskCMP_CM2RS_VIREF_M09D32	(9 << 5)
#define	mskCMP_CM2RS_VIREF_M10D32	(10 << 5)
#define	mskCMP_CM2RS_VIREF_M11D32	(11 << 5)
#define	mskCMP_CM2RS_VIREF_M12D32	(12 << 5)
#define	mskCMP_CM2RS_VIREF_M13D32	(13 << 5)
#define	mskCMP_CM2RS_VIREF_M14D32	(14 << 5)
#define	mskCMP_CM2RS_VIREF_M15D32	(15 << 5)
#define	mskCMP_CM2RS_VIREF_M16D32	(16 << 5)
#define	mskCMP_CM2RS_VIREF_M17D32	(17 << 5)
#define	mskCMP_CM2RS_VIREF_M18D32	(18 << 5)
#define	mskCMP_CM2RS_VIREF_M19D32	(19 << 5)
#define	mskCMP_CM2RS_VIREF_M20D32	(20 << 5)
#define	mskCMP_CM2RS_VIREF_M21D32	(21 << 5)
#define	mskCMP_CM2RS_VIREF_M22D32	(22 << 5)
#define	mskCMP_CM2RS_VIREF_M23D32	(23 << 5)
#define	mskCMP_CM2RS_VIREF_M24D32	(24 << 5)
#define	mskCMP_CM2RS_VIREF_M25D32	(25 << 5)
#define	mskCMP_CM2RS_VIREF_M26D32	(26 << 5)
#define	mskCMP_CM2RS_VIREF_M27D32	(27 << 5)
#define	mskCMP_CM2RS_VIREF_M28D32	(28 << 5)
#define	mskCMP_CM2RS_VIREF_M29D32	(29 << 5)
#define	mskCMP_CM2RS_VIREF_M30D32	(30 << 5)
#define	mskCMP_CM2RS_VIREF_M31D32	(31 << 5)


//CM0OEN, CM1OEN, CM2OEN
#define	CMP_CMnOn_DISABLE					0
#define	CMP_CMnO1_ENABLE					1
#define	CMP_CMnO2_ENABLE					2
#define	CMP_CMnO3_ENABLE					3

#define	mskCMP_CM0On_DISABLE			(CMP_CMnOn_DISABLE << 10)
#define	mskCMP_CM0O1_ENABLE				(CMP_CMnO1_ENABLE << 10)
#define	mskCMP_CM0O2_ENABLE				(CMP_CMnO2_ENABLE << 10)
#define	mskCMP_CM0O3_ENABLE				(CMP_CMnO3_ENABLE << 10)

#define	mskCMP_CM1On_DISABLE			(CMP_CMnOn_DISABLE << 26)
#define	mskCMP_CM1O1_ENABLE				(CMP_CMnO1_ENABLE << 26)
#define	mskCMP_CM1O2_ENABLE				(CMP_CMnO2_ENABLE << 26)
#define	mskCMP_CM1O3_ENABLE				(CMP_CMnO3_ENABLE << 26)

#define	mskCMP_CM2On_DISABLE			(CMP_CMnOn_DISABLE << 10)
#define	mskCMP_CM2O1_ENABLE				(CMP_CMnO1_ENABLE << 10)
#define	mskCMP_CM2O2_ENABLE				(CMP_CMnO2_ENABLE << 10)
#define	mskCMP_CM2O3_ENABLE				(CMP_CMnO3_ENABLE << 10)

//CM0G, CM1G, CM2G
#define	CMP_CMnG_FALLING					0
#define	CMP_CMnG_RISING						1

#define	mskCMP_CM0G_FALLING				(CMP_CMnG_FALLING << 12)
#define	mskCMP_CM0G_RISING				(CMP_CMnG_RISING << 12)

#define	mskCMP_CM1G_FALLING				(CMP_CMnG_FALLING << 28)
#define	mskCMP_CM1G_RISING				(CMP_CMnG_RISING << 28)

#define	mskCMP_CM2G_FALLING				(CMP_CMnG_FALLING << 12)
#define	mskCMP_CM2G_RISING				(CMP_CMnG_RISING << 12)

//CMPIREF
#define	CMP_IREF_VDD							0
#define	CMP_IREF_1P5V							1
#define	CMP_IREF_2V								2
#define	CMP_IREF_3V								3

#define	mskCMP_CMPIREF_VDD				(CMP_IREF_VDD << 1)
#define	mskCMP_CMPIREF_1P5V				(CMP_IREF_1P5V << 1)
#define	mskCMP_CMPIREF_2V					(CMP_IREF_2V << 1)
#define	mskCMP_CMPIREF_3V					(CMP_IREF_3V << 1)
#define	mskCMP_CMPIREFEN_DISABLE	(DISBALE << 0)
#define	mskCMP_CMPIREFEN_ENABLE		(ENABLE << 0)

//CM0IE, CM1IE, CM2IE
#define	mskCMP_CM0IE_DISABLE			(DISABLE << 0)
#define	mskCMP_CM0IE_ENABLE				(ENABLE << 0)
#define	mskCMP_CM1IE_DISABLE			(DISABLE << 1)
#define	mskCMP_CM1IE_ENABLE				(ENABLE << 1) 
#define	mskCMP_CM2IE_DISABLE			(DISABLE << 2)
#define	mskCMP_CM2IE_ENABLE				(ENABLE << 2) 

//CM0IC, CM1IC, CM2IC
#define	mskCMP_CM0IC_ENABLE				(ENABLE << 0)
#define	mskCMP_CM1IC_ENABLE				(ENABLE << 1)
#define	mskCMP_CM2IC_ENABLE				(ENABLE << 2)

/*_____ M A C R O S ________________________________________________________*/

//CMP HCLK Enable/Disable
#define	__CMP_ENABLE_CMPHCLK			SN_SYS1->AHBCLKEN_b.CMPCLKEN = ENABLE;
#define	__CMP_DISABLE_CMPHCLK			SN_SYS1->AHBCLKEN_b.CMPCLKEN = DISABLE;

//CMP0/1/2 Enable/Disable
#define	__CMP0_ENABLE							SN_CMP->CTRL_b.CM0EN = ENABLE;
#define	__CMP0_DISABLE						SN_CMP->CTRL_b.CM0EN = DISABLE;
#define	__CMP1_ENABLE							SN_CMP->CTRL_b.CM1EN = ENABLE;
#define	__CMP1_DISABLE						SN_CMP->CTRL_b.CM1EN = DISABLE;
#define	__CMP2_ENABLE							SN_CMP->CTRL1_b.CM2EN = ENABLE;
#define	__CMP2_DISABLE						SN_CMP->CTRL1_b.CM2EN = DISABLE;

/*_____ D E C L A R A T I O N S ____________________________________________*/
void CMP_init(void);
void CMP_VIREF_Enable(uint32_t);

#endif	/*__SN32F780_CMP_H*/
