#ifndef __SN32F800_DAC_H
#define __SN32F800_DAC_H

/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F800.h>
#include <SN32F800_Def.h>

/*_____ D E F I N I T I O N S ______________________________________________*/
/*
	Base Address: 0x4006 4000 (DAC)
*/

/* DAC Management register <DAC_ADM> (0x00) */

																		//[0:0]DAC0 enable bit
#define mskDAC_DAC0EN_DIS						DISABLE
#define mskDAC_DAC0EN_EN						ENABLE

																		//[1:1]DAC1 enable bit
#define mskDAC_DAC1EN_DIS						DISABLE
#define mskDAC_DAC1EN_EN						ENABLE

																		//[2:2]DAC2 enable bit
#define mskDAC_DAC2EN_DIS						DISABLE
#define mskDAC_DAC2EN_EN						ENABLE

																		//[3:3]DAC3 enable bit
#define mskDAC_DAC3EN_DIS						DISABLE
#define mskDAC_DAC3EN_EN						ENABLE

																		//[8:8]DAC0 output buffer enable bit
#define mskDAC_DAO0BUFEN_DIS				DISABLE
#define mskDAC_DAO0BUFEN_EN					ENABLE

																		//[9:9]DAC1 output buffer enable bit
#define mskDAC_DAO1BUFEN_DIS				DISABLE
#define mskDAC_DAO1BUFEN_EN					ENABLE

																		//[10:10]DAC2 output buffer enable bit
#define mskDAC_DAO2BUFEN_DIS				DISABLE
#define mskDAC_DAO2BUFEN_EN					ENABLE

																		//[11:11]DAC3 output buffer enable bit
#define mskDAC_DAO3BUFEN_DIS				DISABLE
#define mskDAC_DAO3BUFEN_EN					ENABLE

/* DAC internal reference voltage source register <DAC_VIREF> (0x04) */

																		//[1:0]DAC internal reference voltage source
#define DAC_VIREF_DISABLE						0
#define DAC_VIREF_INTERNAL_2V				1
#define DAC_VIREF_INTERNAL_2P5V			2
#define DAC_VIREF_INTERNAL_3V				3

#define mskDAC_VIREF_DISABLE				(DAC_VIREF_DISABLE << 0)
#define mskDAC_VIREF_INTERNAL_2V		(DAC_VIREF_INTERNAL_2V << 0)
#define mskDAC_VIREF_INTERNAL_2P5V	(DAC_VIREF_INTERNAL_2P5V << 0)
#define mskDAC_VIREF_INTERNAL_3V		(DAC_VIREF_INTERNAL_3V << 0)

																		//[17:16]DAC internal reference high voltage select bit
#define DAC_VHS_AVDD								0
#define DAC_VHS_VIREF								1
#define DAC_VHS_ADC									2

#define mskDAC_VHS_AVDD							(DAC_VHS_AVDD << 16)
#define mskDAC_VHS_VIREF						(DAC_VHS_VIREF << 16)
#define mskDAC_VHS_ADC							(DAC_VHS_ADC << 16)

/* DAC clock source register <DAC_CLK> (0x08) */
#define DAC_DAnCKS_DIV1							0
#define DAC_DAnCKS_DIV2							1
#define DAC_DAnCKS_DIV4							2
#define DAC_DAnCKS_DIV8							3
#define DAC_DAnCKS_DIV16						4
#define DAC_DAnCKS_DIV32						5

																		//[2:0]DAC0 clock source divider
#define mskDAC_DA0CKS_DIV1					(DAC_DAnCKS_DIV1 << 0)
#define mskDAC_DA0CKS_DIV2					(DAC_DAnCKS_DIV2 << 0)
#define mskDAC_DA0CKS_DIV4					(DAC_DAnCKS_DIV4 << 0)
#define mskDAC_DA0CKS_DIV8					(DAC_DAnCKS_DIV8 << 0)
#define mskDAC_DA0CKS_DIV16					(DAC_DAnCKS_DIV16 << 0)
#define mskDAC_DA0CKS_DIV32					(DAC_DAnCKS_DIV32 << 0)

																		//[6:4]DAC0 clock source divider
#define mskDAC_DA1CKS_DIV1					(DAC_DAnCKS_DIV1 << 4)
#define mskDAC_DA1CKS_DIV2					(DAC_DAnCKS_DIV2 << 4)
#define mskDAC_DA1CKS_DIV4					(DAC_DAnCKS_DIV4 << 4)
#define mskDAC_DA1CKS_DIV8					(DAC_DAnCKS_DIV8 << 4)
#define mskDAC_DA1CKS_DIV16					(DAC_DAnCKS_DIV16 << 4)
#define mskDAC_DA1CKS_DIV32					(DAC_DAnCKS_DIV32 << 4)

																		//[10:8]DAC0 clock source divider
#define mskDAC_DA2CKS_DIV1					(DAC_DAnCKS_DIV1 << 8)
#define mskDAC_DA2CKS_DIV2					(DAC_DAnCKS_DIV2 << 8)
#define mskDAC_DA2CKS_DIV4					(DAC_DAnCKS_DIV4 << 8)
#define mskDAC_DA2CKS_DIV8					(DAC_DAnCKS_DIV8 << 8)
#define mskDAC_DA2CKS_DIV16					(DAC_DAnCKS_DIV16 << 8)
#define mskDAC_DA2CKS_DIV32					(DAC_DAnCKS_DIV32 << 8)

																		//[14:12]DAC0 clock source divider
#define mskDAC_DA3CKS_DIV1					(DAC_DAnCKS_DIV1 << 12)
#define mskDAC_DA3CKS_DIV2					(DAC_DAnCKS_DIV2 << 12)
#define mskDAC_DA3CKS_DIV4					(DAC_DAnCKS_DIV4 << 12)
#define mskDAC_DA3CKS_DIV8					(DAC_DAnCKS_DIV8 << 12)
#define mskDAC_DA3CKS_DIV16					(DAC_DAnCKS_DIV16 << 12)
#define mskDAC_DA3CKS_DIV32					(DAC_DAnCKS_DIV32 << 12)

/* DAC trigger control register <DAC_TGCTRL> (0x0C) */
#define DAC_DAnTGSEL_PCLK						0
#define DAC_DAnTGSEL_CT16B0_TC			1
#define DAC_DAnTGSEL_CT16B1_TC			2
#define DAC_DAnTGSEL_CT16B2_TC			3
#define DAC_DAnTGSEL_CT16B5_TC			6
#define DAC_DAnTGSEL_SOFTWARE				7

																		//[2:0]DAC0 trigger source select bit
#define mskDAC_DA0TGSEL_PCLK				(DAC_DAnTGSEL_PCLK << 0)
#define mskDAC_DA0TGSEL_CT16B0_TC		(DAC_DAnTGSEL_CT16B0_TC << 0)
#define mskDAC_DA0TGSEL_CT16B1_TC		(DAC_DAnTGSEL_CT16B1_TC << 0)
#define mskDAC_DA0TGSEL_CT16B2_TC		(DAC_DAnTGSEL_CT16B2_TC << 0)
#define mskDAC_DA0TGSEL_CT16B5_TC		(DAC_DAnTGSEL_CT16B5_TC << 0)
#define mskDAC_DA0TGSEL_SOFTWARE		(DAC_DAnTGSEL_SOFTWARE << 0)

																		//[6:4]DAC1 trigger source select bit
#define mskDAC_DA1TGSEL_PCLK				(DAC_DAnTGSEL_PCLK << 4)
#define mskDAC_DA1TGSEL_CT16B0_TC		(DAC_DAnTGSEL_CT16B0_TC << 4)
#define mskDAC_DA1TGSEL_CT16B1_TC		(DAC_DAnTGSEL_CT16B1_TC << 4)
#define mskDAC_DA1TGSEL_CT16B2_TC		(DAC_DAnTGSEL_CT16B2_TC << 4)
#define mskDAC_DA1TGSEL_CT16B5_TC		(DAC_DAnTGSEL_CT16B5_TC << 4)
#define mskDAC_DA1TGSEL_SOFTWARE		(DAC_DAnTGSEL_SOFTWARE << 4)

																		//[10:8]DAC2 trigger source select bit
#define mskDAC_DA2TGSEL_PCLK				(DAC_DAnTGSEL_PCLK << 8)
#define mskDAC_DA2TGSEL_CT16B0_TC		(DAC_DAnTGSEL_CT16B0_TC << 8)
#define mskDAC_DA2TGSEL_CT16B1_TC		(DAC_DAnTGSEL_CT16B1_TC << 8)
#define mskDAC_DA2TGSEL_CT16B2_TC		(DAC_DAnTGSEL_CT16B2_TC << 8)
#define mskDAC_DA2TGSEL_CT16B5_TC		(DAC_DAnTGSEL_CT16B5_TC << 8)
#define mskDAC_DA2TGSEL_SOFTWARE		(DAC_DAnTGSEL_SOFTWARE << 8)

																		//[14:12]DAC3 trigger source select bit
#define mskDAC_DA3TGSEL_PCLK				(DAC_DAnTGSEL_PCLK << 12)
#define mskDAC_DA3TGSEL_CT16B0_TC		(DAC_DAnTGSEL_CT16B0_TC << 12)
#define mskDAC_DA3TGSEL_CT16B1_TC		(DAC_DAnTGSEL_CT16B1_TC << 12)
#define mskDAC_DA3TGSEL_CT16B2_TC		(DAC_DAnTGSEL_CT16B2_TC << 12)
#define mskDAC_DA3TGSEL_CT16B5_TC		(DAC_DAnTGSEL_CT16B5_TC << 12)
#define mskDAC_DA3TGSEL_SOFTWARE		(DAC_DAnTGSEL_SOFTWARE << 12)

																		//[16:16]DAC0 software trigger bit
#define mskDAC_DA0SWTGR_START				(ENABLE << 16)

																		//[17:17]DAC1 software trigger bit
#define mskDAC_DA1SWTGR_START				(ENABLE << 17)

																		//[18:18]DAC2 software trigger bit
#define mskDAC_DA2SWTGR_START				(ENABLE << 18)

																		//[19:19]DAC3 software trigger bit
#define mskDAC_DA3SWTGR_START				(ENABLE << 19)

/* DAC raw interrupt enable register <DAC_IE> (0x20) */
#define mskDAC_DAC0IE_DIS						(DISABLE << 0)
#define mskDAC_DAC0IE_EN						(ENABLE << 0)

#define mskDAC_DAC1IE_DIS						(DISABLE << 1)
#define mskDAC_DAC1IE_EN						(ENABLE << 1)

#define mskDAC_DAC2IE_DIS						(DISABLE << 2)
#define mskDAC_DAC2IE_EN						(ENABLE << 2)

#define mskDAC_DAC3IE_DIS						(DISABLE << 3)
#define mskDAC_DAC3IE_EN						(ENABLE << 3)

/* DAC raw interrupt status register <DAC_RIS/DAC_IC> (0x24/0x28) */
#define mskDAC0IF										(0x1 << 0)
#define mskDAC0IC										mskDAC0IF
#define mskDAC1IF										(0x1 << 1)
#define mskDAC1IC										mskDAC1IF
#define mskDAC2IF										(0x1 << 2)
#define mskDAC2IC										mskDAC2IF
#define mskDAC3IF										(0x1 << 3)
#define mskDAC3IC										mskDAC3IF

typedef struct
{
	uint8_t bDAC_VHS;							//Specifies the DAC internal reference high voltage
	
	uint8_t bDAC_VIREF;						//Specifies the DAC internal reference voltage source
	
	uint8_t bDAC_Clock_Div;				//Specifies the DAC clock source divider
	
	uint8_t bDAC_Clock_Source;		//Specifies the DAC clock source
	
	uint8_t bDAC_IE_Enable;				//Specifies the DAC interrupt is enable or not
	
} SDAC_INIT_TYPE;
	
enum
{
	DAC_Channel0, DAC_Channel1, DAC_Channel2, DAC_Channel3
};

/*_____ M A C R O S ________________________________________________________*/ 
//DAC HCLK Enable/Disable
#define	__DAC_ENABLE_DACHCLK				SN_SYS1->AHBCLKEN_b.DACCLKEN = ENABLE;
#define	__DAC_DISABLE_DACHCLK				SN_SYS1->AHBCLKEN_b.DACCLKEN = DISABLE;

/*_____ D E C L A R A T I O N S ____________________________________________*/
extern SDAC_INIT_TYPE sDAC_InitType;
void DAC_Init(uint8_t bDAC_Ch, SDAC_INIT_TYPE* sDAC_InitStruct);
void DAC_ChannelCtrl(uint8_t bDAC_Ch, uint8_t bDAC_BufEn, uint8_t bDAC_En);
void DAC_SetData(uint8_t bDAC_Ch, uint16_t hwDAC_Data);
void DAC_NvicEnable(void);
void DAC_NvicDisable(void);

#endif	/*__SN32F800_DAC_H*/
