#ifndef __SN32F790_EBI_H
#define __SN32F790_EBI_H

/*_____ I N C L U D E S ____________________________________________________*/
#include <stdint.h>

/*_____ D E F I N I T I O N S ______________________________________________*/
#define	EBI_BANK0_ADD	 0x60000000
#define	EBI_BANK1_ADD	 0x64000000
#define	EBI_BANK2_ADD	 0x68000000
#define	EBI_BANK3_ADD	 0x6C000000

#define BANK0 		0 
#define BANK1   	1 
#define BANK2   	2
#define BANK3   	3

/*---0x4005E000---*/
/*** SYS1 AHB Clock Enable register***/	

#define	EBI_CLK_EN								(0x01<<15)
#define	EBI_CLK_DIS								(0x00<<15)

/*** SYS1 RST Enable register***/
#define	RESET_EBI									(0x01<<4)

/*
EBI Base Address: 0x4003 6000 
*/

/*** EBI Control register***/
//[27:24] 	BK8080MODE0,1,2,3
#define	EBI_BK8080MODE_A1D16 			0			
#define	EBI_BK8080MODE_A1D8  			1
#define mskEBI_8080MODE0_A1D16		(EBI_BK8080MODE_A1D16<<24)
#define	mskEBI_8080MODE0_A1D8		  (EBI_BK8080MODE_A1D8<<24)
#define mskEBI_8080MODE1_A1D16		(EBI_BK8080MODE_A1D16<<25)
#define	mskEBI_8080MODE1_A1D8		  (EBI_BK8080MODE_A1D8<<25)
#define mskEBI_8080MODE2_A1D16		(EBI_BK8080MODE_A1D16<<26)
#define	mskEBI_8080MODE2_A1D8		  (EBI_BK8080MODE_A1D8<<26)
#define mskEBI_8080MODE3_A1D16		(EBI_BK8080MODE_A1D16<<27)
#define	mskEBI_8080MODE3_A1D8		  (EBI_BK8080MODE_A1D8<<27)

//[23:20] 	Idle time 0x0~0xF
#define	EBI_IDLE0T 								0			
#define	EBI_IDLE1T  							1
#define	EBI_IDLE2T 								2			
#define	EBI_IDLE3T  							3
#define	EBI_IDLE4T 								4			
#define	EBI_IDLE5T  							5
#define	EBI_IDLE6T 								6			
#define	EBI_IDLE7T  							7
#define	EBI_IDLE8T 								8			
#define	EBI_IDLE9T  							9
#define	EBI_IDLE10T 							10
#define	EBI_IDLE11T 							11
#define	EBI_IDLE12T 							12
#define	EBI_IDLE13T 							13
#define	EBI_IDLE14T 							14
#define	EBI_IDLE15T 							15
#define mskEBI_IDLE0T		  				(EBI_IDLE0T<<20)
#define mskEBI_IDLE1T		  				(EBI_IDLE1T<<20)
#define mskEBI_IDLE2T		  				(EBI_IDLE2T<<20)
#define mskEBI_IDLE3T		  				(EBI_IDLE3T<<20)
#define mskEBI_IDLE4T		  				(EBI_IDLE4T<<20)
#define mskEBI_IDLE5T		  				(EBI_IDLE5T<<20)
#define mskEBI_IDLE6T		  				(EBI_IDLE6T<<20)
#define mskEBI_IDLE7T		  				(EBI_IDLE7T<<20)
#define mskEBI_IDLE8T		  				(EBI_IDLE8T<<20)
#define mskEBI_IDLE9T		  				(EBI_IDLE9T<<20)
#define mskEBI_IDLE10T		  			(EBI_IDLE10T<<20)
#define mskEBI_IDLE11T		  			(EBI_IDLE11T<<20)
#define mskEBI_IDLE12T		  			(EBI_IDLE12T<<20)
#define mskEBI_IDLE13T		  			(EBI_IDLE13T<<20)
#define mskEBI_IDLE14T		  			(EBI_IDLE14T<<20)
#define mskEBI_IDLE15T		  			(EBI_IDLE15T<<20)

//[19:16] 	ARDYEN0,1,2,3
#define	EBI_DISABLE_ARDY 					0			
#define	EBI_ENABLE_ARDY  					1
#define mskEBI_ARDY0_EN		  			(EBI_ENABLE_ARDY<<16)
#define	mskEBI_ARDY0_DIS				  (EBI_DISABLE_ARDY<<16)
#define mskEBI_ARDY1_EN		  			(EBI_ENABLE_ARDY<<17)
#define	mskEBI_ARDY1_DIS				  (EBI_DISABLE_ARDY<<17)
#define mskEBI_ARDY2_EN		  			(EBI_ENABLE_ARDY<<18)
#define	mskEBI_ARDY2_DIS				  (EBI_DISABLE_ARDY<<18)
#define mskEBI_ARDY3_EN		  			(EBI_ENABLE_ARDY<<19)
#define	mskEBI_ARDY3_DIS				  (EBI_DISABLE_ARDY<<19)

//[15:12] 	BCEN0,1,2,3
#define	EBI_DISABLE_BC 						0			
#define	EBI_ENABLE_BC  						1
#define mskEBI_BC0_EN		  				(EBI_ENABLE_BC<<12)
#define	mskEBI_BC0_DIS				 	 	(EBI_DISABLE_BC<<12)
#define mskEBI_BC1_EN		  				(EBI_ENABLE_BC<<13)
#define	mskEBI_BC1_DIS				  	(EBI_DISABLE_BC<<13)
#define mskEBI_BC2_EN		  				(EBI_ENABLE_BC<<14)
#define	mskEBI_BC2_DIS				  	(EBI_DISABLE_BC<<14)
#define mskEBI_BC3_EN		  				(EBI_ENABLE_BC<<15)
#define	mskEBI_BC3_DIS				  	(EBI_DISABLE_BC<<15)

//[11:8] 	BANK0,1,2,3
#define	EBI_DISABLE_BANK 					0			
#define	EBI_ENABLE_BANK  					1
#define mskEBI_BANK0_EN		  			(EBI_ENABLE_BANK<<8)
#define	mskEBI_BANK0_DIS				  (EBI_DISABLE_BANK<<8)
#define mskEBI_BANK1_EN		  			(EBI_ENABLE_BANK<<9)
#define	mskEBI_BANK1_DIS				  (EBI_DISABLE_BANK<<9)
#define mskEBI_BANK2_EN		  			(EBI_ENABLE_BANK<<10)
#define	mskEBI_BANK2_DIS				  (EBI_DISABLE_BANK<<10)
#define mskEBI_BANK3_EN		  			(EBI_ENABLE_BANK<<11)
#define	mskEBI_BANK3_DIS				  (EBI_DISABLE_BANK<<11)

//[7:0] 	MODE0,1,2,3
#define	EBI_MODE_AND8 						0			
#define	EBI_MODE_AND16  					1
#define	EBI_MODE_AND16ALE 				2			
#define	EBI_MODE_8080  						3
#define mskEBI_BANK0_AND8		  		(EBI_MODE_AND8<<0)
#define	mskEBI_BANK0_AND16				(EBI_MODE_AND16<<0)
#define mskEBI_BANK0_AND16ALE		  (EBI_MODE_AND16ALE<<0)
#define	mskEBI_BANK0_8080				  (EBI_MODE_8080<<0)
#define mskEBI_BANK1_AND8		  		(EBI_MODE_AND8<<2)
#define	mskEBI_BANK1_AND16				(EBI_MODE_AND16<<2)
#define mskEBI_BANK1_AND16ALE		  (EBI_MODE_AND16ALE<<2)
#define	mskEBI_BANK1_8080				  (EBI_MODE_8080<<2)
#define mskEBI_BANK2_AND8		  		(EBI_MODE_AND8<<4)
#define	mskEBI_BANK2_AND16				(EBI_MODE_AND16<<4)
#define mskEBI_BANK2_AND16ALE		  (EBI_MODE_AND16ALE<<4)
#define	mskEBI_BANK2_8080				  (EBI_MODE_8080<<4)
#define mskEBI_BANK3_AND8		  		(EBI_MODE_AND8<<6)
#define	mskEBI_BANK3_AND16				(EBI_MODE_AND16<<6)
#define mskEBI_BANK3_AND16ALE		  (EBI_MODE_AND16ALE<<6)
#define	mskEBI_BANK3_8080				  (EBI_MODE_8080<<6)


/*** EBI Address Length Control register***/
//[15:12] 	AL3  	0x0~0xA
//[11:8] 		AL2		0x0~0xA
//[7:4] 		AL1		0x0~0xA
//[3:0] 		AL0		0x0~0xA
#define	EBI_ADD16PIN 							0			
#define	EBI_ADD17PIN  						1
#define	EBI_ADD18PIN 							2			
#define	EBI_ADD19PIN  						3
#define	EBI_ADD20PIN 							4			
#define	EBI_ADD21PIN  						5
#define	EBI_ADD22PIN 							6			
#define	EBI_ADD23PIN  						7
#define	EBI_ADD24PIN 							8			
#define	EBI_ADD25PIN  						9
#define	EBI_ADD26PIN 							10			


/*** EBI Status register***/
//[8:8] EBISMRST
#define	EBI_NORMAL	 							0
#define	EBI_SMRST	 								1
#define mskEBI_NORMAL			  			(EBI_NORMAL<<8)
#define	mskEBI_SMRST				  		(EBI_SMRST<<8)
//[4:4] EBIARDY
#define	EBI_ARDY_BUSY							0			
#define	EBI_ARDY_READY	 					1
#define mskEBI_ARDY_BUSY					(EBI_ARDY_BUSY<<4)
#define	mskEBI_ARDY_READY					(EBI_ARDY_READY<<4)
//[0:0] EBIBUSY
#define	EBI_IDLE									0			
#define	EBI_BUSY	 								1
#define mskEBI_IDLE			  				(EBI_IDLE)
#define	mskEBI_BUSY			  				(EBI_BUSY)

/*** EBI Address Timing register0,1,2,3***/
/*** EBI Read Timing register0,1,2,3***/
/*** EBI Write Timing register0,1,2,3***/
#define	EBI_0T 										0			
#define	EBI_1T  									1
#define	EBI_2T 										2			
#define	EBI_3T  									3
#define	EBI_4T 										4			
#define	EBI_5T  									5
#define	EBI_6T 										6			
#define	EBI_7T  									7
#define	EBI_8T 										8			
#define	EBI_9T  									9
#define	EBI_10T 									10
#define	EBI_11T 									11
#define	EBI_12T 									12
#define	EBI_13T 									13
#define	EBI_14T 									14
#define	EBI_15T 									15

/*** EBI Polarity register***/
//[4:4] ARDYPOL
#define	EBI_ARDY_ACTIVELOW				0			
#define	EBI_ARDY_ACTIVEHIGH	 			1
#define mskEBI_ARDY_ACTIVELOW			(EBI_ARDY_ACTIVELOW<<4)
#define	mskEBI_ARDY_ACTIVEHIGH		(EBI_ARDY_ACTIVEHIGH<<4)

/*** EBI Interrupt Enable register***/
//[5:5] DMATCIE
#define	EBI_DMATCIE_DIS						0			
#define	EBI_DMATCIE_EN	 					1
#define mskEBI_DMATCIE_DIS				(EBI_DMATCIE_DIS<<5)
#define	mskEBI_DMATCIE_EN					(EBI_DMATCIE_EN<<5)
//[4:4] DMAHTIE
#define	EBI_DMAHTIE_DIS						0			
#define	EBI_DMAHTIE_EN	 					1
#define mskEBI_DMAHTIE_DIS				(EBI_DMAHTIE_DIS<<4)
#define	mskEBI_DMAHTIE_EN					(EBI_DMAHTIE_EN<<4)
//[3:3] RWERREN
#define	EBI_RWERREN_DIS						0			
#define	EBI_RWERREN_EN	 					1
#define mskEBI_RWERREN_DIS				(EBI_RWERREN_DIS<<3)
#define	mskEBI_RWERREN_EN					(EBI_RWERREN_EN<<3)
//[2:2] SMRSTEN
#define	EBI_SMRSTEN_DIS						0			
#define	EBI_SMRSTEN_EN	 					1
#define mskEBI_SMRSTEN_DIS				(EBI_SMRSTEN_DIS<<2)
#define	mskEBI_SMRSTEN_EN					(EBI_SMRSTEN_EN<<2)
//[1:1] ACCDISEN
#define	EBI_ACCDISEN_DIS					0			
#define	EBI_ACCDISEN_EN	 					1
#define mskEBI_ACCDISEN_DIS				(EBI_ACCDISEN_DIS<<1)
#define	mskEBI_ACCDISEN_EN				(EBI_ACCDISEN_EN<<1)
//[0:0] ARDYTOEN
#define	EBI_ARDYTOEN_DIS					0			
#define	EBI_ARDYTOEN_EN	 					1
#define mskEBI_ARDYTOEN_DIS				(EBI_ARDYTOEN_DIS)
#define	mskEBI_ARDYTOEN_EN				(EBI_ARDYTOEN_EN)

/*** EBI Interrupt Flag register************/
//[5:5] DMATCIF
#define	EBI_RIS_DMATCIF						1
#define	mskEBI_RIS_DMATCIF				(EBI_RIS_DMATCIF<<5)
//[4:4] DMAHTIF
#define	EBI_RIS_DMAHTIF						1
#define	mskEBI_RIS_DMAHTIF				(EBI_RIS_DMAHTIF<<4)
//[3:3] RWERRIF	
#define	EBI_RIS_RWERRIF				 	  1
#define	mskEBI_RIS_RWERRIF				(EBI_RIS_RWERRIF<<3)
//[2:2] SMRSTIF	
#define	EBI_RIS_SMRSTIF				 		1
#define	mskEBI_RIS_SMRSTIF				(EBI_RIS_SMRSTIF<<2)
//[1:1] ACCDISIF
#define	EBI_RIS_ACCDISIF				 	1
#define	mskEBI_RIS_ACCDISIF				(EBI_RIS_ACCDISIF<<1)
//[0:0] ARDYTOIF
#define	EBI_RIS_ARDYTOIF				  1
#define	mskEBI_RIS_ARDYTOIF				(EBI_RIS_ARDYTOIF)

/*** EBI Interrupt Clear register************/
//[5:5] DMATCIC
#define	EBI_RIS_DMATCIC						1
#define	mskEBI_RIS_DMATCIC				(EBI_RIS_DMATCIC<<5)
//[4:4] DMAHTIC
#define	EBI_RIS_DMAHTIC						1
#define	mskEBI_RIS_DMAHTIC				(EBI_RIS_DMAHTIC<<4)
//[3:3] RWERRIC	
#define	EBI_RIS_RWERRIC				 	  1
#define	mskEBI_RIS_RWERRIC				(EBI_RIS_RWERRIC<<3)
//[2:2] SMRSTIC	
#define	EBI_RIS_SMRSTIC				 		1
#define	mskEBI_RIS_SMRSTIC				(EBI_RIS_SMRSTIC<<2)
//[1:1] ACCDISIC
#define	EBI_RIS_ACCDISIC				 	1
#define	mskEBI_RIS_ACCDISIC				(EBI_RIS_ACCDISIC<<1)
//[0:0] ARDYTOIC
#define	EBI_RIS_ARDYTOIC				  1
#define	mskEBI_RIS_ARDYTOIC				(EBI_RIS_ARDYTOIC)


/*** EBI DMA Control register************/
//[3:2] BANKSELECT
#define	EBI_DMA_BANK0				  		0
#define	EBI_DMA_BANK1				  		1
#define	EBI_DMA_BANK2				 			2
#define	EBI_DMA_BANK3				  		3
#define	mskEBI_DMA_BANK0					(EBI_DMA_BANK0<<2)
#define	mskEBI_DMA_BANK1					(EBI_DMA_BANK1<<2)
#define	mskEBI_DMA_BANK2					(EBI_DMA_BANK2<<2)
#define	mskEBI_DMA_BANK3					(EBI_DMA_BANK3<<2)
//[1:1] SPISELECT	
#define	EBI_DMA_SPI0						  0
#define	EBI_DMA_SPI1						  1
#define	mskEBI_DMA_SPI0						(EBI_DMA_SPI0<<1)
#define	mskEBI_DMA_SPI1						(EBI_DMA_SPI1<<1)
//[0:0] DMAEN
#define	EBI_DMA_DIS				 				0
#define	EBI_DMA_EN								1
#define	mskEBI_DMA_DIS						(EBI_DMA_DIS)
#define	mskEBI_DMA_EN							(EBI_DMA_EN)

/*** EBI DMA Number of Data Transfer register************/
/*** EBI DMA Number of Half Data Transfer register************/
/*** EBI DMA Current Transfer Data Counter register************/

void EBI_8080Init(uint8_t bBank, uint8_t bMode);
void EBI_8080DMA(uint8_t bSPI, uint8_t bBANK, uint8_t bInterruptMode);
void EBI_Clear_Intflag(void);
void EBI_Interrupt_Enable(void);
void EBI_Interrupt_Disable(void);	
void EBI_8080Write_CMD_16B(uint16_t hwCMD);
void EBI_8080Write_Data_16B(uint16_t hwData);

void DMA_full_data(uint32_t wFlashAdd, uint32_t wSize);
void DMA_one_data(uint32_t wFlashAdd, uint32_t wSize);
void DMA_full_data_add_IO_toggle(uint32_t wFlashAdd, uint32_t wSize);
void DMA_Disable_Test(void);

extern uint32_t wREG_Add;
extern uint32_t wRAM_Add;	

extern uint8_t bARDYTO_Flag;
extern uint8_t bRWERR_Flag;
extern uint8_t bSMRST_Flag;
extern uint8_t bACCDIS_Flag;
extern uint8_t bDMATC_Flag;
extern uint8_t bDMAHT_Flag;

#endif	/*__SN32F790_EBI_H*/
