/******************** (C) COPYRIGHT 2021 SONiX *******************************
* COMPANY:		SONiX
* DATE:				2021/06
* AUTHOR:			SA1
* IC:					SN32F780/790
*____________________________________________________________________________
*	REVISION	Date				User		Description
*	1.0				2020/06/24	SA1			1. First version released
*																2. Compatible to CMSIS DFP Architecture in Keil MDK v5.X (http://www.keil.com/dd2/pack/)
*																3. Run HexConvert to generate bin file and show checksum after building.
*	1.1				2020/11/20	SA1			1. Update Flash.h and system_SN32F790.c
*																2. Update SYS0_SystemClockSwitch and SYS0_SystemCoreClockUpdate functions in SYS_con_drive.c
*	1.4				2021/06/08	SA1			1. Update SYS_con_drive.h and SYS0_LvdControl function.
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL 
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN 
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/

/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F790.h>
#include <SN32F700_Def.h>
#include ".\System\SYS_con_drive.h"

/*_____ D E C L A R A T I O N S ____________________________________________*/
void PFPA_Init(void);
void NotPinOut_GPIO_init(void);


/*_____ D E F I N I T I O N S ______________________________________________*/
#ifndef	SN32F799					//Do NOT Remove or Modify!!!
	#error Please install SONiX.SN32F7_DFP.1.5.0.pack or version >= 1.5.0
#endif
#define	PKG						SN32F799				//User SHALL modify the package on demand (SN32F799, SN32F798, SN32F797, SN32F795, SN32F7951)

#define	SWITCH_CASE		SYS0_CLK_IHRC		//SYS0_CLK_IHRC, SYS0_CLK_ILRC, SYS0_CLK_EHS, SYS0_CLK_ELS, SYS0_CLK_PLL

/*_____ M A C R O S ________________________________________________________*/

/*_____ F U N C T I O N S __________________________________________________*/

/*****************************************************************************
* Function		: main
* Description	: Clock Switch & Clockout demo code. 
* Input			: None
* Output		: None
* Return		: None
* Note			: None
*****************************************************************************/
int	main(void)
{
	PFPA_Init();										//User shall set PFPA if used, do NOT remove!!!

	//1. User SHALL define PKG on demand.
	//2. User SHALL set the status of the GPIO which are NOT pin-out to input pull-up.
	NotPinOut_GPIO_init();

	//--------------------------------------------------------------------------
	//User Code starts HERE!!!

	#if (SWITCH_CASE == SYS0_CLK_IHRC)
	SYS0_EnableIHRC(ENABLE);
	SYS0_SystemClockSwitch(SYS0_SYSCLK_IHRC, SYS0_AHBPRE_DIV1, SYS0_SYSCLK_DIV1);
	SYS0_SystemCoreClockUpdate(12000000);		//Note: Must be called with Exact HCLK frequency, Do NOT remove!!!
	#endif
	
	#if (SWITCH_CASE == SYS0_CLK_ILRC)
	SYS0_SystemClockSwitch(SYS0_SYSCLK_ILRC, SYS0_AHBPRE_DIV2, SYS0_SYSCLK_DIV1);
	SYS0_SystemCoreClockUpdate(16000);				//Note: Must be called with Exact HCLK frequency, Do NOT remove!!!
	#endif
	
	#if (SWITCH_CASE == SYS0_CLK_EHS)
	SYS0_EnableEHSXtal(16);
	SYS0_SystemClockSwitch(SYS0_CLK_EHS, SYS0_AHBPRE_DIV1, SYS0_SYSCLK_DIV1);
	SYS0_SystemCoreClockUpdate(16000000);		//Note: Must be called with Exact HCLK frequency, Do NOT remove!!!
	#endif
	
	#if (SWITCH_CASE == SYS0_CLK_ELS)
	SYS0_EnableELSXtal();
	SYS0_SystemClockSwitch(SYS0_CLK_ELS, SYS0_AHBPRE_DIV1, SYS0_SYSCLK_DIV1);
	SYS0_SystemCoreClockUpdate(32768);			//Note: Must be called with Exact HCLK frequency, Do NOT remove!!!
	#endif
	
	#if (SWITCH_CASE == SYS0_CLK_PLL)
	//Example: EHS=16MHz ---> PLL=48MHz
	//Note: User shall call SYS0_EnableEHSXtal or SYS0_EnableIHRC to make sure
  //			the clock source of PLL is enabled and ready.	
	SYS0_EnableEHSXtal(16);
	SYS0_EnablePLL(SYS0_PLL_M6, SYS0_PLL_P2, SYS0_PLL_CLOCK_EHS);
	SYS0_SystemClockSwitch(SYS0_CLK_PLL, SYS0_AHBPRE_DIV1, SYS0_SYSCLK_DIV1P5);
	SYS0_SystemCoreClockUpdate(32000000);		//Note: Must be called with Exact HCLK frequency, Do NOT remove!!!
	#endif

	//Clockout (Optional)
	SYS1_EnableClockout(SYS1_CLOCKOUT_HCLK, SYS1_CLOCKOUT_DIV2);

	while (1);
}

/*****************************************************************************
* Function		: NotPinOut_GPIO_init
* Description	: Set the status of the GPIO which are NOT pin-out to input pull-up. 
* Input				: None
* Output			: None
* Return			: None
* Note				: 1. User SHALL define PKG on demand.
*****************************************************************************/
void NotPinOut_GPIO_init(void)
{
#if (PKG == SN32F798) || (PKG == SN32F788)
	//set P0.8~P0.9, P0.16~P0.19 to input pull-up
	SN_GPIO0->CFG = 0xAAA0AAAA;
	SN_GPIO0->CFG1 = 0x0;
	//set P1.16~P1.19 to input pull-up
	SN_GPIO1->CFG1 = 0x0;
	//set P3.14~P3.19 to input pull-up
	SN_GPIO3->CFG = 0x0AAAAAAA;
	SN_GPIO3->CFG1 = 0x0;
#elif (PKG == SN32F797)
	//set P0.6~P0.9, P0.12~P0.19 to input pull-up
	SN_GPIO0->CFG = 0x00A00AAA;
	SN_GPIO0->CFG1 = 0x0;
	//set P1.6~P1.7, P1.10~P1.11, P1.16~P1.19 to input pull-up
	SN_GPIO1->CFG = 0xAA0A0AAA;
	SN_GPIO1->CFG1 = 0x0;
	//set P2.10~P2.15 to input pull-up
	SN_GPIO2->CFG = 0x000AAAAA;
	//set P3.14~P3.19 to input pull-up
	SN_GPIO3->CFG = 0x0AAAAAAA;
	SN_GPIO3->CFG1 = 0x0;
#elif (PKG == SN32F795)
	//set P0.0~0.P0.2, P0.4, P0.6~P0.9, P0.12~P0.19 to input pull-up
	SN_GPIO0->CFG = 0x00A00880;
	SN_GPIO0->CFG1 = 0x0;
	//set P1.4~P1.7, P1.9~P1.19 to input pull-up
	SN_GPIO1->CFG = 0x000200AA;
	SN_GPIO1->CFG1 = 0x0;
	//set P2.10~P2.15 to input pull-up
	SN_GPIO2->CFG = 0x000AAAAA;
	//set P3.8~P3.11, P3.14~P3.19 to input pull-up
	SN_GPIO3->CFG = 0x0A00AAAA;
	SN_GPIO3->CFG1 = 0x0;
#elif (PKG == SN32F7951)
	//set P0.0~0.P0.4, P0.6~P0.9, P0.13~P0.19 to input pull-up
	SN_GPIO0->CFG = 0x02A00800;
	SN_GPIO0->CFG1 = 0x0;
	//set P1.4~P1.7, P1.9~P1.11, P1.16~P1.19 to input pull-up
	SN_GPIO1->CFG = 0xAA0200AA;
	SN_GPIO1->CFG1 = 0x0;
	//set P2.9~P2.15 to input pull-up
	SN_GPIO2->CFG = 0x0002AAAA;
	//set P3.3~P3.4, P3.8~P3.11, P3.14~P3.19 to input pull-up
	SN_GPIO3->CFG = 0x0A00A82A;
	SN_GPIO3->CFG1 = 0x0;
#endif
}

/*****************************************************************************
* Function		: HardFault_Handler
* Description	: ISR of Hard fault interrupt
* Input			: None
* Output		: None
* Return		: None
* Note			: None
*****************************************************************************/
__irq void HardFault_Handler(void)
{
	NVIC_SystemReset();
}
