
;------------------------------------------------------------------------------
;  CHIP: SNPD1722
;  Revision History
;  
;  V01   2021/12/02	
;------------------------------------------------------------------------------
.ASSEMBLY RedWrt_FORMAT    1
.Assembly	INC_VER		1
.Assembly	ASM_FORMAT	1
.Assembly	RAM_Size	1024

.Assembly	INSTRUMENT	SNPD1722
.Assembly	BIT_FILE	SNPD1722

.Assembly	OTP_BODY_SIZE	0x2000
.Assembly	USER_ROM_SIZE	0x1FF8
.Assembly	MASK_TEST_CODE	0x0000, 0x0000, 0x0000, 0x0000

.Assembly	PGM_TYPE	6
.Assembly	CHIP_ID		0x6180
.Assembly	command		Enable_ORG4_7, RBANK_LIMIT 

.Assembly	Port_Pins	8, 0, 0, 0, 7, 0
; Code Option 0x0FFF
.Assembly	OPTION		0		Fix_High
.Assembly	OPTION		1		Security	Enable	Disable
.Assembly	OPTION		2		Fcpu		Fosc/2 Fosc/4 Fosc/8 x
.Help
{
	Fcpu		: 	"Only Effective for HIGH Clock"
}
.Assembly	OPTION		4		Fix_High
.Assembly	OPTION		5		Fix_High
.Assembly	OPTION		6		Fix_High
.Assembly	OPTION		7		Fix_High

.Assembly	OPTION		8		Watch_Dog	Always_On x x x x Enable x x x x Disable x x x x x
.Assembly	OPTION		12		Reset_Pin       P46 	Reset
.Assembly	OPTION		13		Rst_Length  	No 	128*ILRC
.Assembly	OPTION		14		Fix_High
.Assembly	OPTION		15		Fix_High

; Code Option 0x0FFE
.Assembly	OPTION		16		Fix_Low
.Assembly	OPTION		17		Fix_High
.Assembly	OPTION		18		Fix_Low
.Assembly	OPTION		19		Fix_High
.Assembly	OPTION		20		Fix_High
.Assembly	OPTION		21		Fix_Low
.Assembly	OPTION		22		Fix_High
.Assembly	OPTION		23		Fix_Low

.Assembly	OPTION		24		Fix_Low
.Assembly	OPTION		25		Fix_High
.Assembly	OPTION		26		Fix_Low
.Assembly	OPTION		27		Fix_High
.Assembly	OPTION		28 : 31		Fix_High

; Code Option 0x0FFD
;IHRC		 10-bit	32:41	
.Assembly	OPTION		32		Fix_High
.Assembly	OPTION		33		Fix_High
.Assembly	OPTION		34		Fix_High
.Assembly	OPTION		35		Fix_High
.Assembly	OPTION		36		Fix_High
.Assembly	OPTION		37 		Fix_High
.Assembly	OPTION		38 		Fix_High
.Assembly	OPTION		39 		Fix_High
.Assembly	OPTION		40 		Fix_High
.Assembly	OPTION		41 		Fix_High


.Assembly	OPTION		42 		Hold_Clock	Enable	Disable	
					
.Assembly	OPTION		43		Fix_Low				
;LVD24		 4-bit	44:47	
.Assembly	OPTION		44 		Fix_High
.Assembly	OPTION		45 		Fix_High
.Assembly	OPTION		46 		Fix_High
.Assembly	OPTION		47		Fix_High		

; Code Option 0x0FFC
.Assembly	OPTION		48 : 63		Fix_High	


.Assembly	OPTION		2ffh

L		EQU		80H
H		EQU		81H
R		EQU		82H
Z		EQU		83H
Y		EQU		84H
	
PFLAG		EQU		86H
FPOR		EQU_R		PFLAG.7
FWDT		EQU_R		PFLAG.6
FRST		EQU_R		PFLAG.5
FSTKOV		EQU_R		PFLAG.4
FC		EQU		PFLAG.2
FDC		EQU		PFLAG.1
FZ		EQU		PFLAG.0

RBANK		EQU		87H
FRBNKS2		EQU		RBANK.2
FRBNKS1		EQU		RBANK.1
FRBNKS0		EQU		RBANK.0


@HL		EQU		90H
@YZ		EQU		91H
PCL		EQU		93H
PCH		EQU		94H
OSCM		EQU		95H
FOTPMDCTRL	EQU		OSCM.7
FCPUM1		EQU		OSCM.4
FCPUM0		EQU		OSCM.3
FCLKMD		EQU		OSCM.2
FSTPHX		EQU		OSCM.1

WDTR		EQU_W		96H


INTRQ		EQU		97H
FNDTIRQ		EQU		INTRQ.7
FADCIRQ		EQU		INTRQ.6
FTC0IRQ		EQU		INTRQ.5
FSIOIRQ 	EQU		INTRQ.3	
FWAKEIRQ	EQU		INTRQ.2
FTC1IRQ		EQU		INTRQ.1
FP00IRQ  	EQU		INTRQ.0

INTEN		EQU		99H
FNDTIEN		EQU		INTEN.7
FADCIEN		EQU		INTEN.6
FTC0IEN		EQU		INTEN.5
FSIOIEN 	EQU		INTEN.3
FWAKEIEN	EQU		INTEN.2
FTC1IEN		EQU		INTEN.1
FP00IEN  	EQU		INTEN.0

ADT		EQU		09AH
FADT4 	 	EQU		ADT.4
FADT3 	 	EQU		ADT.3
FADT2 	 	EQU		ADT.2
FADT1 	 	EQU		ADT.1
FADT0	  	EQU		ADT.0

ADM		EQU		09BH
FADENB		EQU		ADM.7
FADS		EQU		ADM.6
FEOC		EQU		ADM.5
FCHS3		EQU		ADM.3
FCHS2		EQU		ADM.2
FCHS1		EQU		ADM.1
FCHS0		EQU		ADM.0

ADB		EQU_R		09CH
FADB11		EQU_R		ADB.7
FADB10		EQU_R		ADB.6
FADB9		EQU_R		ADB.5
FADB8		EQU_R		ADB.4
FADB7		EQU_R		ADB.3
FADB6		EQU_R		ADB.2
FADB5		EQU_R		ADB.1
FADB4		EQU_R		ADB.0

ADR		EQU		09DH
FGCHS		EQU		ADR.6		
FADCKS1		EQU		ADR.5
FADCKS0		EQU		ADR.4
FADB3		EQU_R		ADR.3
FADB2		EQU_R		ADR.2
FADB1		EQU_R		ADR.1
FADB0		EQU_R		ADR.0

	
VREFH		EQU		09EH
FVHS2		EQU_R		ADR.2
FVHS1		EQU_R		ADR.1
FVHS0		EQU_R		ADR.0

PEDGE		EQU		09FH
FP00G1		EQU		PEDGE.1
FP00G0		EQU		PEDGE.0
	
P0M		EQU		0A0H
FP07M		EQU		P0M.7
FP06M		EQU		P0M.6
FP05M		EQU		P0M.5
FP04M		EQU		P0M.4
FP03M		EQU		P0M.3
FP02M		EQU		P0M.2	
FP01M		EQU		P0M.1
FP00M		EQU		P0M.0

P4M		EQU		0A1H
FP45M		EQU		P4M.5
FP44M		EQU		P4M.4
FP43M		EQU		P4M.3
FP42M		EQU		P4M.2
FP41M		EQU		P4M.1
FP40M		EQU		P4M.0

P0		EQU 		0A5H
FP07		EQU 		P0.7
FP06		EQU 		P0.6
FP05		EQU 		P0.5
FP04		EQU 		P0.4
FP03		EQU 		P0.3
FP02		EQU 		P0.2
FP01		EQU 		P0.1
FP00		EQU 		P0.0

P4		EQU		0A6H
FP46		EQU		P4.6
FP45		EQU		P4.5
FP44		EQU		P4.4
FP43		EQU		P4.3
FP42		EQU		P4.2
FP41		EQU		P4.1
FP40		EQU		P4.0

P0UR        	EQU     	0AAH
FP07R		EQU		P0UR.7
FP06R		EQU		P0UR.6
FP05R		EQU		P0UR.5
FP04R		EQU		P0UR.4
FP03R		EQU		P0UR.3
FP02R		EQU		P0UR.2		
FP01R		EQU		P0UR.1
FP00R		EQU		P0UR.0

P4UR       	EQU    		0ABH
FP45R		EQU		P4UR.5
FP44R		EQU		P4UR.4
FP43R		EQU		P4UR.3
FP42R		EQU		P4UR.2
FP41R		EQU		P4UR.1
FP40R		EQU		P4UR.0

P4DR       	EQU     	0ACH
FP46DR		EQU		P4DR.6



P0CON        	EQU     	0ADH
FP07CON		EQU		P0CON.7
FP06CON		EQU		P0CON.6
FP05CON		EQU		P0CON.5
FP04CON		EQU		P0CON.4
FP03CON		EQU		P0CON.3
FP02CON		EQU		P0CON.2		
FP01CON		EQU		P0CON.1
FP00CON		EQU		P0CON.0

P4CON        	EQU     	0AEH
FP46CON		EQU		P4CON.6
FP45CON		EQU		P4CON.5
FP44CON		EQU		P4CON.4
FP43CON		EQU		P4CON.3
FP42CON		EQU		P4CON.2		
FP41CON		EQU		P4CON.1
FP40CON		EQU		P4CON.0

TC0M		EQU		0B8H
FTC0ENB		EQU		TC0M.7
FTC0RATE2	EQU		TC0M.6
FTC0RATE1	EQU		TC0M.5
FTC0RATE0	EQU		TC0M.4
FALOAD0		EQU 		TC0M.2
    		
TC0C		EQU		0B9H	
TC0R		EQU_W		0BAH
	
	
SPSTA        	EQU     	0DDH
FSPIF		EQU		SPSTA.7
FWCOL		EQU		SPSTA.6
FSSERR		EQU		SPSTA.5
FMODF		EQU		SPSTA.4
FSPIMX		EQU		SPSTA.0

SPCON		EQU		0DEH
FSPR2		EQU		SPCON.7
FSPEN		EQU		SPCON.6
FSPDIS		EQU		SPCON.5
FMSTR		EQU		SPCON.4
FCPOL		EQU		SPCON.3 	   		
FCPHA   	EQU 		SPCON.2
FSPR1   	EQU 		SPCON.1
FSPR0	  	EQU 		SPCON.0 

SPDAT		EQU		0DFH


TC1M		EQU		0E0H
FTC1ENB		EQU		TC1M.7
FTC1RATE2	EQU		TC1M.6
FTC1RATE1	EQU		TC1M.5
FTC1RATE0	EQU		TC1M.4
FTC1CKS0   	EQU 		TC1M.2
    		
TC1C		EQU		0E1H	
TC1R		EQU_W		0E2H


T_LVD24		EQU		0E8H	
FT_LVD24_3	EQU		T_LVD24.3 	   		
FT_LVD24_2   	EQU 		T_LVD24.2
FT_LVD24_1   	EQU 		T_LVD24.1
FT_LVD24_0	EQU 		T_LVD24.0 

T_ADCREF	EQU		0E9H	
FADCREF5	EQU		T_ADCREF.5 	   		
FADCREF4   	EQU 		T_ADCREF.4
FADCREF3	EQU		T_ADCREF.3 	   		
FADCREF2   	EQU 		T_ADCREF.2
FADCREF1   	EQU 		T_ADCREF.1
FADCREF0	EQU 		T_ADCREF.0 

	
AIPCTRL		EQU		0ECH
FEN_IHRCOUT	EQU 		AIPCTRL.0 

T_IHRC_L	EQU		0EDH	
FIHRC7		EQU		T_IHRC_L.7 	   		
FIHRC6   	EQU 		T_IHRC_L.6
FIHRC5		EQU		T_IHRC_L.5 	   		
FIHRC4   	EQU 		T_IHRC_L.4
FIHRC3		EQU		T_IHRC_L.3 	   		
FIHRC2   	EQU 		T_IHRC_L.2
FIHRC1   	EQU 		T_IHRC_L.1
FIHRC0		EQU 		T_IHRC_L.0 

T_IHRC_H	EQU		0EEH	
FIHRC9		EQU		T_IHRC_H.1 	   		
FIHRC8   	EQU 		T_IHRC_H.0




STKP		EQU		0EFH
FGIE		EQU		STKP.7
FSTKPB2		EQU		STKP.2
FSTKPB1		EQU		STKP.1
FSTKPB0		EQU		STKP.0


STK7L		EQU		0F0h
STK7H		EQU		0F1h
STK6L		EQU		0F2h
STK6H		EQU		0F3h
STK5L		EQU		0F4h
STK5H		EQU		0F5h
STK4L		EQU		0F6h
STK4H		EQU		0F7h
STK3L		EQU		0F8h
STK3H		EQU		0F9h
STK2L		EQU		0FAh
STK2H		EQU		0FBh
STK1L		EQU		0FCh
STK1H		EQU		0FDh
STK0L		EQU		0FEh
STK0H		EQU		0FFh
	

; -----------------------------------------------------
; Clear watchdog macro. 
;  
; Total Cycle: 2

@RST_WDT	macro
	MOV    A, #0x5A
	B0MOV  WDTR, A
endm
; -----------------------------------------------------
; Sleep Mode control macro for compatibility in S8KD-2 ICE
;  
; Total Cycle: 1

SleepMode	macro	
	B0BSET	FCPUM0
endm
; -----------------------------------------------------
; Green Mode control macro for compatibility in S8KD-2 ICE
;  
; Total Cycle: 3

GreenMode	macro	
	B0BSET	FCPUM1
	NOP
	NOP
endm
; -----------------------------------------------------
; Slow Mode control macro for compatibility in S8KD-2 ICE
;  
; Total Cycle: 2

SlowMode	macro	
	B0BSET	FCLKMD
	B0BSET	FSTPHX
endm
; -----------------------------------------------------
;  Slow mode to Normal Mode control macro for compatibility in S8KD-2 ICE
;  
; Total Cycle: 5

Slow2Normal	macro	
	B0BCLR	FSTPHX
	NOP
	NOP
	NOP
	B0BCLR	FCLKMD
endm
; -----------------------------------------------------
;  Slow mode to Normal Mode control macro for compatibility in S8KD-2 ICE
;  
; Total Cycle: 5

	Set_P3_Input_Pullup	macro	
    DW	0x2D00 		;MOV	a, #0x00	; Port 3: Input pull-up high
    DW 	0x2FC3 		;b0MOV	P3M,a
    DW	0x2DFF 		;MOV	a, #0xFF
    DW	0x2FD3 		;b0MOV	P3,a
    DW	0x2FE3 		;b0MOV	P3UR,a
	endm
; -----------------------------------------------------
	
.TEXT
{
	//{{SONIX_OPTION_RULE
        
	ENDP
	//}}SONIX_OPTION_RULE
}