
;------------------------------------------------------------------------------
;  CHIP: SN8P2957, OTP Only.
;  Revision History:
;  V1.0  09/04/2012  First issue - Modified from 2929
;  V1.1  09/11/2012  
;		                 1. Modify Watch_Dog CodeOption
;  V1.2  12/07/2012  
;		                 1. Modify ADCK register to ADCKS
;  V1.3  12/10/2012  
;		                 1. Modify VBIASM1.6
;------------------------------------------------------------------------------
.Assembly	INC_VER		1
.Assembly RedWrt_FORMAT   1
.Assembly	ASM_FORMAT	1
.Assembly	RAM_Size	0C0H

.Assembly	INSTRUMENT	SN8P2957
.Assembly	BIT_FILE	SN8P2957

.Assembly	OTP_BODY_SIZE	0x1000
.Assembly	USER_ROM_SIZE	0x0FFC

.Assembly	COMMAND		Enable_ORG4_7, Enable_ISP	; Limit org 4~7, unavailible for user
.Assembly	PGM_TYPE	6				; 2's Program Type			
.Assembly	MASK_TEST_CODE	0x0000, 0x000, 0x0000, 0x0000
.Assembly	Port_Pins	8, 2, 0, 0, 0, 0, 0
.Assembly	LCD_Size	12, 4
.Assembly	CHIP_ID		0x9780

; Code Option 0x0FFF
.Assembly	OPTION			0		Fix_High	
.Assembly	OPTION			1		Security	Enable	Disable
.Assembly	OPTION			2		High_Clk_DIV	Fhosc/4 Fhosc/8 
.Assembly	OPTION			3   : 7		Fix_High	
.Assembly	OPTION			8 	        Watch_Dog	x x x x x Enable x x x x Disable x x x x Always_On 
.Assembly	OPTION			12  : 15	Fix_High			

; Code Option 0x0FFE
.Assembly	OPTION			16		Fix_Low
.Assembly	OPTION			17		Fix_High
.Assembly	OPTION			18		Fix_Low
.Assembly	OPTION			19		Fix_High
.Assembly	OPTION			20		Fix_High
.Assembly	OPTION			21		Fix_Low
.Assembly	OPTION			22		Fix_High
.Assembly	OPTION			23		Fix_Low
.Assembly	OPTION			24		Fix_Low
.Assembly	OPTION			25		Fix_High
.Assembly	OPTION			26		Fix_Low
.Assembly	OPTION			27 : 31		Fix_High

; Code Option 0x0FFD
.Assembly	OPTION			32 : 40		Fix_High ;(IHRC_CAL_Data)
.Assembly	OPTION			41 : 47		Fix_High

; Code Option 0x0FFC
.Assembly	OPTION			48 : 63		Fix_High

.Assembly	OPTION			2ffh

;------------------------------------------------------------------------------

	L		EQU		0x80
	H		EQU		0x81
	R		EQU		0x82
	Z		EQU		0x83
	Y		EQU		0x84
	
	PFLAG			EQU		0x86
		FC		EQU		PFLAG.2
		FDC		EQU		PFLAG.1
		FZ		EQU		PFLAG.0
		
	RBANK			EQU		0x87
		FRBNKS3		EQU		RBANK.3
		FRBNKS2		EQU		RBANK.2
		FRBNKS1		EQU		RBANK.1
		FRBNKS0		EQU		RBANK.0

	LCDM1			EQU		0x89
		FLCDBNK		EQU		LCDM1.7
		FLCDMOD2	EQU		LCDM1.6
		FLCDMOD1	EQU		LCDM1.5
		FLCDMOD0	EQU		LCDM1.4
		FLCDENB		EQU		LCDM1.3
		FLCDBIAS	EQU		LCDM1.2		
		FLCDRATE	EQU		LCDM1.1
		FLCDCLK		EQU		LCDM1.0	

	LCDM2			EQU		0x8A	
		FVAR1			EQU		LCDM2.7
	  FVAR0			EQU		LCDM2.6
	  FDISQ			EQU		LCDM2.5
	  FVPPINTL	EQU		LCDM2.3
	  FVCP2			EQU		LCDM2.2
		FVCP1			EQU		LCDM2.1
		FVCP0			EQU		LCDM2.0
						
	VREG			EQU		0x90
		FBGRENB		EQU		VREG.7
		FACMSEL		EQU		VREG.6
		FACMENB		EQU		VREG.5
		FAVESEL		EQU		VREG.4
		FAVENB		EQU		VREG.3
		FAVDDREN	EQU		VREG.2

	PSW			EQU		0x91
		FPSWGEN		EQU		PSW.4
		FPSW4EN		EQU		PSW.3
		FPSW3EN		EQU		PSW.2
		FPSW2EN		EQU		PSW.1
		FPSW1EN		EQU		PSW.0

	AMPM1			EQU		0x92
		FDTENB		EQU		AMPM1.7
		FDTSEL		EQU		AMPM1.6
		FMUXN2		EQU		AMPM1.5
		FMUXN1		EQU		AMPM1.4
		FMUXN0		EQU		AMPM1.3
		FMUXP2		EQU		AMPM1.2
		FMUXP1		EQU		AMPM1.1
		FMUXP0		EQU		AMPM1.0

	AMPM2			EQU		0x93
		FGR				EQU		AMPM2.6
		FGX				EQU		AMPM2.5
		FGS2			EQU		AMPM2.4
		FGS1			EQU		AMPM2.3
		FGS0			EQU		AMPM2.2
		FAMPCKS		EQU		AMPM2.1
		FAMPENB		EQU		AMPM2.0

	ADCM1			EQU		0x94
		FRVS			EQU		ADCM1.7
		FIRVS2		EQU		ADCM1.6
		FIRVS1		EQU		ADCM1.5
		FIRVS0		EQU		ADCM1.4
		FADGN2		EQU		ADCM1.3
		FADGN1		EQU		ADCM1.2
		FADGN0		EQU		ADCM1.1
		FADCENB		EQU		ADCM1.0
				
	ADCM2			EQU		0X95
		FOSR2			EQU		ADCM2.7
		FOSR1			EQU		ADCM2.6
		FOSR0			EQU		ADCM2.5
		FADCKS1		EQU		ADCM2.4
		FADCKS0		EQU		ADCM2.3
		FOFSEL1		EQU		ADCM2.2
		FOFSEL0		EQU		ADCM2.1
		FDRDY			EQU		ADCM2.0

	LBTM			EQU		0x96
		FP11IO		EQU		LBTM.6
		FLBTSEL3	EQU		LBTM.5
		FLBTSEL2	EQU		LBTM.4
		FLBTSEL1	EQU		LBTM.3
		FLBTSEL0	EQU		LBTM.2
		FLBTO			EQU		LBTM.1
		FLBTENB		EQU		LBTM.0

	ADCDH			EQU_R		0x97
	ADCDM			EQU_R		0x98
	ADCDL			EQU_R		0x99		

	VBIASM1		EQU		0x9A
		FVBMOD1		EQU		VBIASM1.7
		FVBMOD0		EQU		VBIASM1.6
		FVBIT11		EQU		VBIASM1.3
		FVBIT10		EQU		VBIASM1.2
		FVBIT09		EQU		VBIASM1.1
		FVBIT08		EQU		VBIASM1.0

	VBIASM2		EQU		0x9B
		FVBIT07		EQU		VBIASM2.7
		FVBIT06		EQU		VBIASM2.6
		FVBIT05		EQU		VBIASM2.5
		FVBIT04		EQU		VBIASM2.4
		FVBIT03		EQU		VBIASM2.3
		FVBIT02		EQU		VBIASM2.2
		FVBIT01		EQU		VBIASM2.1
		FVBIT00		EQU		VBIASM2.0

	BZM			EQU		0x9C
		FBZF2			EQU		BZM.3
		FBZF1			EQU		BZM.2
		FBZF0			EQU		BZM.1
		FBZOENB		EQU		BZM.0
				
	ROMADRH			EQU		0xA0
		FVPPCHK		EQU_R		ROMADRH.7
		FROMADR11	EQU		ROMADRH.3
		FROMADR10	EQU		ROMADRH.2
		FROMADR9	EQU		ROMADRH.1
		FROMADR8	EQU		ROMADRH.0
			
	ROMADRL			EQU		0xA1	
		FROMADR7	EQU		ROMADRL.7
		FROMADR6	EQU		ROMADRL.6
		FROMADR5	EQU		ROMADRL.5
		FROMADR4	EQU		ROMADRL.4
		FROMADR3	EQU		ROMADRL.3
		FROMADR2	EQU		ROMADRL.2
		FROMADR1	EQU		ROMADRL.1
		FROMADR0	EQU		ROMADRL.0
		
	ROMDAH			EQU		0xA2
		FROMDA15	EQU		ROMDAH.7
		FROMDA14	EQU		ROMDAH.6
		FROMDA13	EQU		ROMDAH.5
		FROMDA12	EQU		ROMDAH.4
		FROMDA11	EQU		ROMDAH.3
		FROMDA10	EQU		ROMDAH.2
		FROMDA9		EQU		ROMDAH.1
		FROMDA8		EQU		ROMDAH.0
		
	ROMDAL			EQU		0xA3
		FROMDA7		EQU		ROMDAL.7
		FROMDA6		EQU		ROMDAL.6
		FROMDA5		EQU		ROMDAL.5
		FROMDA4		EQU		ROMDAL.4
		FROMDA3		EQU		ROMDAL.3
		FROMDA2		EQU		ROMDAL.2
		FROMDA1		EQU		ROMDAL.1
		FROMDA0		EQU		ROMDAL.0

	ROMCNT			EQU_W		0xA4
		ROMCNT1		EQU_W		ROMCNT.1
		ROMCNT0		EQU_W		ROMCNT.0	

	P0M			EQU		0xB8
		FP07M		EQU		P0M.7
		FP06M		EQU		P0M.6
		FP05M		EQU		P0M.5
		FP04M		EQU		P0M.4
		FP03M		EQU		P0M.3
		FP02M		EQU		P0M.2
		FP01M		EQU		P0M.1
		FP00M		EQU		P0M.0

	PEDGE			EQU		0xBF
		FP00G1		EQU		PEDGE.4
		FP00G0		EQU		PEDGE.3

	P1M			EQU		0xC1
		FP11M		EQU		P1M.1
		FP10M		EQU		P1M.0

	INTRQ			EQU		0C8H
		FADCIRQ		EQU		INTRQ.7
		FT0IRQ		EQU		INTRQ.4
		FP00IRQ		EQU		INTRQ.0

	INTEN			EQU		0C9H
		FADCIEN		EQU		INTEN.7
		FT0IEN		EQU		INTEN.4
		FP00IEN		EQU		INTEN.0

	OSCM			EQU		0xCA
		FCPUM1		EQU		OSCM.4
		FCPUM0		EQU		OSCM.3
		FCLKMD		EQU		OSCM.2
		FSTPHX		EQU		OSCM.1
		
	WDTR			EQU_W	0xCC	
	PCL				EQU		0xCE
	PCH				EQU		0xCF

	P0				EQU		0xD0
		FP07			EQU		P0.7
		FP06			EQU		P0.6
		FP05			EQU		P0.5
		FP04			EQU		P0.4
		FP03			EQU		P0.3
		FP02			EQU		P0.2
		FP01			EQU		P0.1
		FP00			EQU		P0.0

	P1				EQU		0xD1
		FP11			EQU		P1.1
		FP10			EQU		P1.0
		
	T0M				EQU		0xD8
		FT0ENB		EQU		T0M.7
		FT0RATE2	EQU		T0M.6
		FT0RATE1	EQU		T0M.5
		FT0RATE0	EQU		T0M.4

	T0C				EQU		0xD9

	STKP			EQU		0xDF
		FGIE			EQU		STKP.7
		FSTKPB2		EQU		STKP.2
		FSTKPB1		EQU		STKP.1
		FSTKPB0		EQU		STKP.0

	P0UR			EQU_W	0xE0
		FP07R			EQU_W	P0UR.7
		FP06R			EQU_W	P0UR.6
		FP05R			EQU_W	P0UR.5
		FP04R			EQU_W	P0UR.4
		FP03R			EQU_W	P0UR.3
		FP02R			EQU_W	P0UR.2
		FP01R			EQU_W	P0UR.1
		FP00R			EQU_W	P0UR.0

	P1UR			EQU_W	0xE1
		FP11R			EQU_W	P1UR.1
		FP10R			EQU_W	P1UR.0

	@YZ				EQU		0xE7	
	
	STK7L			EQU		0F0h
	STK7H			EQU		0F1h
	STK6L			EQU		0F2h
	STK6H			EQU		0F3h
	STK5L			EQU		0F4h
	STK5H			EQU		0F5h
	STK4L			EQU		0F6h
	STK4H			EQU		0F7h
	STK3L			EQU		0F8h
	STK3H			EQU		0F9h
	STK2L			EQU		0FAh
	STK2H			EQU		0FBh
	STK1L			EQU		0FCh
	STK1H			EQU		0FDh
	STK0L			EQU		0FEh
	STK0H			EQU		0FFh
	
; -----------------------------------------------------
; Clear watchdog macro for compatibility in S8KD-2 ICE
;  
; Total Cycle: 2 

	@RST_WDT	macro		
 		   MOV  A, #0x5A
		   B0MOV  WDTR, A
	endm

; -----------------------------------------------------
; Sleep Mode control macro for compatibility in S8KD-2 ICE
;  
; Total Cycle: 1

	SleepMode	macro	
		B0BSET	FCPUM0
	endm

; -----------------------------------------------------
; Green Mode control macro for compatibility in S8KD-2 ICE
;  
; Total Cycle: 3

	GreenMode	macro	
		B0BSET	FCPUM1
		NOP
		NOP
	endm
	
; -----------------------------------------------------
; Slow Mode control macro for compatibility in S8KD-2 ICE
;  
; Total Cycle: 2

	SLowMode	macro	
		B0BSET	FCLKMD
		B0BSET	FSPTHX
	endm

; -----------------------------------------------------
;  Slow mode to Normal Mode control macro for compatibility in S8KD-2 ICE
;  
; Total Cycle: 5

	Slow2Normal	macro	
		B0BCLR	FSPTHX
		NOP
		NOP
		NOP
		B0BCLR	FCLKMD
	endm
	
; -----------------------------------------------------
;  ISP ROM-Write with Internal VPP 6.9V Generation macro for compatibility in S8KD-2 ICE
;  Occupied Register: A,Y,Z,R  
;  execution time: 40ms(ISP_OK), 30ms(ISP_Fail)
;  Output status: R_Register (ISP_OK: R=0x5AH;   ISP_Fail: R=0xA5H)
	
; -----------------------------------------------------	
.TEXT
{
	//{{SONIX_OPTION_RULE
        
	ENDP
	//}}SONIX_OPTION_RULE
}