/******************** (C) COPYRIGHT 2022 SONiX *******************************
* COMPANY:		SONiX
* DATE:				2022/11
* AUTHOR:			SA1
* IC:					SN32F700B
*____________________________________________________________________________
*	REVISION	Date				User		Description
*	1.0				2015/08/25	SA1			1. First version released
*																2. Compatible to CMSIS DFP Architecture in Keil MDK v5.X (http://www.keil.com/dd2/pack/)
*																3. Run HexConvert to generate bin file and show checksum after building.
*	1.2				2016/12/02	SA1			1. Fix SPI0_Init & SSP0_InterruptEnable
*	1.3				2017/06/05	SA1			1. Fix SPI0_Init
*	1.4				2017/07/14	SA1			1. Update system_SN32F700B.c to V1.0.3
*																2. Fix __FLASH_LPM_PLL_MODE in Flash.h
*	2.0				2018/01/26	SA1			1. Add NotPinOut_GPIO_init to set the status of the GPIO which are NOT pin-out to input pull-up.
*																2. Add CodeOption_SN32F700B.s to modify Code option, please modify with Configuration Wizard, 
*																	 and Strongly recommend to keep CS0 for debugging with SN-LINK.
*	2.2				2018/10/05	SA1			1. Remove CodeOption_SN32F700B.s, please contact SONiX FAE if needed.
*	2.5				2019/05/31	SA1			1. Remove SSP0_InterruptEnable function.
*	2.7				2019/12/31	SA1			1. Update system_SN32F700B.c to V1.1.0
*	3.0				2022/11/11	SA1			1. Update system_SN32F700B.c to V2.0.0
*																2. Update Flash.h
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL 
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN 
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/

/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F700B.h>
#include <SN32F700_Def.h>
#include "Interface\SPI\SPI.h"
#include "Utility\Utility.h"


/*_____ D E C L A R A T I O N S ____________________________________________*/
void	NotPinOut_GPIO_init(void);

void SPI0_NBytesTxRx(uint32_t N_Bytes);

/*_____ D E F I N I T I O N S ______________________________________________*/
#ifndef	SN32F707B					//Do NOT Remove or Modify!!!
	#error Please install SONiX.SN32F7_DFP.1.4.3.pack or version >= 1.4.3
#endif
#define		PKG						SN32F707B		//User SHALL modify the package on demand (SN32F707B, SN32F706B, SN32F705B, SN32F7051B, SN32F704B, SN32F702B)


#define		SPI_TEST_CNT	32

uint16_t	hwSPI_Tx_Fifo[SPI_TEST_CNT];
uint16_t	hwSPI_Rx_Fifo[SPI_TEST_CNT];


/*_____ M A C R O S ________________________________________________________*/


/*_____ F U N C T I O N S __________________________________________________*/

/*****************************************************************************
* Function		: main
* Description	: SPI0 is master. (Connect MISO0 & MOIS0) 
								Exapmle Mode is SPI (CPHA=0, CPOL=0, MLS=0).
								Change mode by setting FORMAT, CPHA, CPOL, MLSB.
* Input			: None
* Output		: None
* Return		: None
* Note			: Connect MISO0 and MOSI0 
*****************************************************************************/
int	main (void)
{
	uint32_t	i=0;
	uint32_t	j=0;	

	//User can configure System Clock with Configuration Wizard in system_SN32F700B.c
	SystemInit();
	SystemCoreClockUpdate();				//Must call for SN32F700B, Please do NOT remove!!!

	//Note: User can refer to ClockSwitch sample code to switch various HCLK if needed.

	//1. User SHALL define PKG on demand.
	//2. User SHALL set the status of the GPIO which are NOT pin-out to input pull-up.
	NotPinOut_GPIO_init();

	//--------------------------------------------------------------------------
	//User Code starts HERE!!!

	//System Interface Init
	SPI0_Init();

	//Write TX FIFO
	for(i=0;i<SPI_TEST_CNT;i++)
	{
		hwSPI_Tx_Fifo[i] = i;
	}	

	//Start Transmission
	j = SPI_TEST_CNT;

	SPI0_NBytesTxRx(j);

	//Check data 
	for(i=0;i<j;i++)
	{
		if(hwSPI_Tx_Fifo[i] != hwSPI_Rx_Fifo[i])
		{
			while(1);	//Error
		}		
	}

	while(1); //Pass
}


/***************************************************************************************************************
* Function		: SIP0_NBytesTxRx
* Description	:
* Input			: hwSPI_Tx_Fifo
* Output		: hwSPI_Rx_Fifo
* Return		: None
* Note			: Avoid all of the interrupts which may make FW can't fill in TX FIFO (SN_SPI0->DATA=...) in time.
***************************************************************************************************************/
void SPI0_NBytesTxRx(uint32_t N_Bytes)
{
	uint32_t  wSPI_Send_Pointer = 0;
	uint32_t  wSPI_Get_Pointer = 0;

	while(wSPI_Send_Pointer != N_Bytes)
	{
		__SPI0_CLR_SEL0;																			//SEL is low
		SN_SPI0->DATA = hwSPI_Tx_Fifo[wSPI_Send_Pointer++];
		while (!(SN_SPI0->STAT & mskSSP_TXFIFOTHF));	//TX Half-Empty
		if(!(SN_SPI0->STAT & mskSSP_RX_EMPTY))								//Check having any data in RXFIFO
		{	
			hwSPI_Rx_Fifo[wSPI_Get_Pointer++] = SN_SPI0->DATA;
		}
	}	

	while(1)
	{
		while(SN_SPI0->STAT & mskSSP_RX_EMPTY); //Get all remaining data
		hwSPI_Rx_Fifo[wSPI_Get_Pointer++] = SN_SPI0->DATA;

		if(wSPI_Get_Pointer == N_Bytes)
		{
			break;
		}
	}
	while(SN_SPI0->STAT & mskSSP_BUSY);

	__SPI0_SET_SEL0;										//SEL is high
	__SPI0_FIFO_RESET;
}

/*****************************************************************************
* Function		: NotPinOut_GPIO_init
* Description	: Set the status of the GPIO which are NOT pin-out to input pull-up. 
* Input				: None
* Output			: None
* Return			: None
* Note				: 1. User SHALL define PKG on demand.
*****************************************************************************/
void	NotPinOut_GPIO_init(void)
{
#if (PKG == SN32F706B)
	//set P0.0~P0.1 to input pull-up
	SN_GPIO0->CFG = 0xAAAAA0;
#elif (PKG == SN32F705B)
	//set P0.0~P0.1 to input pull-up
	SN_GPIO0->CFG = 0x00AAAAA0;
	//set P1.5, P1.8~P1.11 to input pull-up
	SN_GPIO1->CFG = 0x0000A2AA;
	//set P2.5~P2.9 to input pull-up
	SN_GPIO2->CFG = 0x000002AA;
	//set P3.0~P3.3 to input pull-up
	SN_GPIO3->CFG = 0x000AAA00;
#elif (PKG == SN32F7051B)
	//set P0.6~P0.7 to input pull-up
	SN_GPIO0->CFG = 0x00AA0AAA;
	//set P1.5, P1.8~P1.11 to input pull-up
	SN_GPIO1->CFG = 0x0000A2AA;
	//set P2.8~P2.9 to input pull-up
	SN_GPIO2->CFG = 0x0000AAAA;
	//set P3.0~P3.5 to input pull-up
	SN_GPIO3->CFG = 0x000AA000;
#elif (PKG == SN32F704B)
	//set P0.0~P0.1, P0.3 to input pull-up
	SN_GPIO0->CFG = 0x00AAAA20;
	//set P1.5, P1.8~P1.11 to input pull-up
	SN_GPIO1->CFG = 0x0000A2AA;
	//set P2.2~P2.9 to input pull-up
	SN_GPIO2->CFG = 0x0000000A;
	//set P3.0~P3.3 to input pull-up
	SN_GPIO3->CFG = 0x000AAA00;
#elif (PKG == SN32F702B)
	//set P0.3~P0.9 to input pull-up
	SN_GPIO0->CFG = 0x00A0002A;
	//set P1.5, P1.8, P1.10~P1.11 to input pull-up
	SN_GPIO1->CFG = 0x0008A2AA;
	//set P2.3~P2.9 to input pull-up
	SN_GPIO2->CFG = 0x0000002A;
	//set P3.0~P3.5, P3.7~P3.9 to input pull-up
	SN_GPIO3->CFG = 0x00002000;
#endif
}

/*****************************************************************************
* Function		: HardFault_Handler
* Description	: ISR of Hard fault interrupt
* Input			: None
* Output		: None
* Return		: None
* Note			: None
*****************************************************************************/
__irq void HardFault_Handler(void)
{
	NVIC_SystemReset();
}

