#ifndef __SPI_H__
#define __SPI_H__
/*_____ I N C L U D E S _________________________________*/
#include <SN8F5762.h>

/*_____ F U N C T I O N S _______________________________*/
void GPIO_Initialization(void);
void SPI_init(clk,type,spi_interrupt);
void clk_select(uint8_t clk_cmd);
void type_select(uint8_t type_cmd);
void SPI_EN(uint8_t interrupt_cmd);

uint8_t SPI_data(uint8_t bSend_data);
/*_____ D E F I N I T I O N S ___________________________*/
extern uint8_t bTX_buffer;
extern uint8_t bRX_buffer;




//===========================//
//** 				SPSTA						 //
//===========================//

#define SPIF			  (0x01U<<7)
#define WCOL			  (0x01U<<6)
#define SSERR	 			(0x01U<<5)
#define MODF		 		(0x01U<<4)
#define SPIMX		 		(0x01U<<0)

//===========================//
//** 				SPCON						 //
//===========================//
#define mskSPCON_SPEN   	 		(0x01U<<6)
#define mskSPCON_SSDIS   			(0x01U<<5)  // SSN pin disable
#define mskSPCON_MASTER    		(0x01U<<4)	// MASTER MODE

#define mskSPCON_MODE1	(0x00U<<2)	// SPI_Type0 : CPOL = 0, CPHA = 0 
#define mskSPCON_MODE2	(0x01U<<2)	// SPI_Type1 : CPOL = 0, CPHA = 1
#define mskSPCON_MODE3	(0x02U<<2)	// SPI_Type2 : CPOL = 1, CPHA = 0 
#define mskSPCON_MODE4	(0x03U<<2)	// SPI_Type3 : CPOL = 1, CPHA = 1 

#define mskSPCON_SPR_DIV2			(0x00U<<0)		//fclk/2
#define mskSPCON_SPR_DIV4			(0x01U<<0)		//fclk/4
#define mskSPCON_SPR_DIV8			(0x02U<<0)		//fclk/8
#define mskSPCON_SPR_DIV16		(0x03U<<0)		//fclk/16

#define mskSPCON_SPR_DIV32		(0x80U<<0)		//fclk/32
#define mskSPCON_SPR_DIV64		(0x81U<<0)		//fclk/64
#define mskSPCON_SPR_DIV128		(0x82U<<0)		//fclk/128




/*_____ M A C R O S _____________________________________*/
#define  IO_PORT0_OUTPUT_LOW        P0M |= 0xFF;    P0 &= 0x00;
#define  IO_PORT1_OUTPUT_LOW        P1M |= 0xFF;    P1 &= 0x00;
#define  IO_PORT2_OUTPUT_LOW        P2M |= 0xFF;    P2 &= 0x00;

#define  SET_SSN_LOW 	P00=0;
#define  SET_SSN_HIGH P00=1;

#endif  /*	__SPI_H__	*/