/*_____ I N C L U D E S _________________________________*/
#include "SPI.h"

/*_____ F U N C T I O N S _______________________________*/

/*_____ D E F I N I T I O N S ___________________________*/

/*_____ D E C L A R A T I O N S _________________________*/
uint8_t bTX_complete=0,bRX_complete=0;
uint8_t bTX_buffer=0,bRX_buffer=0;
uint8_t clk,type;
//uint8_t bTX_data=0,bRX_data=0;

/*_____ M A C R O S _____________________________________*/


/**
 * @brief This function will initialize the SPI.
 * @param clk_select: \n
 *        \t 0x00 : SPI_RATE_FCPUDIV2 (4 MHz) \n
 *        \t 0x01 : SPI_RATE_FCPUDIV4 (2 MHz) \n
 *        \t 0x02 : SPI_RATE_FCPUDIV8 (1 MHz) \n
 *        \t 0x03 : SPI_RATE_FCPUDIV16 (500	KMHz) \n
 *        \t 0x80 : SPI_RATE_FCPUDIV32 (250 KHz) \n
 *        \t 0x81 : SPI_RATE_FCPUDIV64 (125 KHz) \n
 *        \t 0x82 : SPI_RATE_FCPUDIV128 (62.5 KHz) \n
 * @param type_select: Clock phase for edge sampling and clock polarity selection setting.
 *              \t SPI_Type0 : CPHA = 0, CPOL = 0 \n
 *              \t SPI_Type1 : CPHA = 0, CPOL = 1 \n
 *              \t SPI_Type2 : CPHA = 1, CPOL = 0 \n
 *              \t SPI_Type3 : CPHA = 1, CPOL = 1
 * @param SPI_EN: Base on Master setting
 *              \t spi_interrupt  0x00  interrupt disable \n
 *							\t spi_interrupt  0x01  interrupt enable  \n
 * @return None
 */
void SPI_init(clk,type,spi_interrupt)
{
	//SSN &SCK & MOSI=OUTPUT , MISO=INPUT;
	P0M &= ~(0x80);
	
	clk_select(clk);
	type_select(type);
	SPI_EN(spi_interrupt);
	SPSTA |= SPIMX;
}
void clk_select(uint8_t clk_cmd)
{
	switch(clk_cmd)
	{
		case 0x00:
			clk=mskSPCON_SPR_DIV2;	// Fcpu/2
			break;
		case 0x01:
			clk=mskSPCON_SPR_DIV4;	// Fcpu/4
			break;
		case 0x02:
			clk=mskSPCON_SPR_DIV8;	// Fcpu/8
			break;
		case 0x03:
			clk=mskSPCON_SPR_DIV16;	// Fcpu/16
			break;
		case 0x04:
			clk=mskSPCON_SPR_DIV32;	// Fcpu/32
			break;
		case 0x05:
			clk=mskSPCON_SPR_DIV64;	// Fcpu/64
			break;
		case 0x06:
			clk=mskSPCON_SPR_DIV128;	// Fcpu/128
			break;	
	}
}
void type_select(uint8_t type_cmd)
{
	switch(type_cmd)
	{
		case 0x00:
			type=mskSPCON_MODE1;	// SPI_Type0 : CPOL = 0, CPHA = 0 
			break;
		case 0x01:
			type=mskSPCON_MODE2;	// SPI_Type1 : CPOL = 0, CPHA = 1
			break;
		case 0x02:
			type=mskSPCON_MODE3;	// SPI_Type2 : CPOL = 1, CPHA = 0
			break;
		case 0x03:
			type=mskSPCON_MODE4;	// SPI_Type3 : CPOL = 1, CPHA = 1 
			break;
	}
}
void SPI_EN(uint8_t interrupt_cmd)
{
		//P04=SSN,P05=SCK,P06=MOSI,P07=MISO  
		//SPI Enalbe ,SPI MASTER MODE,SSDIS DISABLE
		SPCON &=0x00;
		SPCON = mskSPCON_SPEN | mskSPCON_MASTER| mskSPCON_SSDIS;
		SPCON |= clk|type;
		switch(interrupt_cmd)
		{
			case 0x00:
				ESPI=0;	//SPI interrupt disalbe
				EAL=0;	// global interrupt disalbe
				break;
			case 0x01:
				ESPI=1;	//SPI interrupt enalbe
				EAL=1;	// global interrupt enalbe
				break;
		}
}
/**
 *	@Brief		Send SPI data
 *	@param		uint8_t bSend_data
 *	@retval		bSPI_RxData
 */
uint8_t SPI_data(uint8_t bSend_data) 
{
	
	do{
		bTX_buffer=bSend_data;
		SET_SSN_LOW
		SPDAT=bTX_buffer;
		WDTR = 0x5A;
	}while((SPSTA&&WCOL)==1);

	while((SPSTA&&SPIF)==0)
	{
			WDTR = 0x5A;	
	}
			
		bRX_buffer=SPDAT;
		return bRX_buffer;
}

