A51 MACRO ASSEMBLER  OPTIONS_SN8F5835                                                     04/27/2022 11:38:43 PAGE     1


MACRO ASSEMBLER A51 V8.02c
OBJECT MODULE PLACED IN .\Objects\OPTIONS_SN8F5835.obj
ASSEMBLER INVOKED BY: C:\Keil_v5\C51\BIN\A51.EXE OPTIONS_SN8F5835.A51 SET(SMALL) DEBUG PRINT(.\Listings\OPTIONS_SN8F5835
                      .lst) OBJECT(.\Objects\OPTIONS_SN8F5835.obj) EP

LOC  OBJ            LINE     SOURCE

                       1     $nomod51 
                       2     ;------------------------------------------------------------------------------
                       3     ;
                       4     ;  Copyright (c) 2019 SONiX Technology Co., Ltd.
                       5     ;  Version 1.0 - SN8F5835, SN8F5834, SN8F5833. Add code option address for MP5
                       6     ;  Version 1.1 - Modify CPU Clock Rate option.
                       7     ;  Version 1.2 - Add CRC region define.
                       8     ;  *** <<< Use Configuration Wizard in Context Menu >>> ***
                       9     ;------------------------------------------------------------------------------
                      10     ;
                      11     ;  This preference, such as watchdog, external reset pin, and clock source, is preloaded 
                      12     ;  during the microcontroller's power-on. It is strongly recommanded to use configuration 
                      13     ;  wizard to set these parameters up appropriately.
                      14     ;
                      15     ;------------------------------------------------------------------------------
  8000                16     ROM_SIZE                EQU             0x8000
                      17     ;
                      18     ;       <o.0..1> Program Memory Security <0x03=> Security Disable <0x02=> Security Enable <
                             0x00=> Security Configuration
  0003                19             SECURITY_SET    EQU     0x03            ;       {0x7FFF}
                      20     ;   <i> Security Disable: all address ROM data can be accessed. 
                      21     ;   <i> Security Enable: all address ROM data are protected.
                      22     ;   <i> Security Configuration: all address ROM data are protected expect address 0x7E00 ~ 
                             0x7FBF ROM data can be accessed.
                      23     ;
                      24     ;   <o.2> ISP Program Area  <0x01=> All Page <0x00=> Page 504~ Page 510
  0004                25         ISP_EN_SET    EQU     0x04          ;       {0x7FFF}
                      26     ;   <i> All Page: all address can perform ISP function.
                      27     ;   <i> Page 504 ~ Page 510: only address 0x7E00 ~ 0x7FBF can perform ISP function.
                      28     
                      29     ;   <h> CPU Clock
                      30     
                      31     ;   <o.3..4> CPU Clock Source <0x03=> IHRC 32 MHz <0x01=> X'tal 12 MHz <0x00=> X'tal 4 MHz 
                             <0x02=> External Clock
  0018                32         CLOCKSRC_SET    EQU     0x18                ;       {0x7FFB}
                      33     ;   <i> IHRC 32 MHz: on-chip internal clock.
                      34     ;   <i> X'tal 12 MHz: off-chip crystal between 8 MHz and 16 MHz.
                      35     ;   <i> X'tal 4 MHz: off-chip crystal between 1 MHz and 8 MHz.
                      36     ;   <i> External Clock: external clock input from XIN pin.
                      37     
                      38     ;   <o.5..7> CPU Clock Rate for IHRC 32MHz  <0x00=> Fhosc/128 <0x01=> Fhosc/64 <0x02=> Fhos
                             c/32 <0x03=> Fhosc/16 <0x04=> Fhosc/8 <0x05=> Fhosc/4
  00A0                39         IHRC32M_CLOCKRATE_SET    EQU     0xA0               ;       {0x7FFB}
                      40     ;   <i> FCPU for IHRC 32MHz is Fhosc/4~Fhosc/128.
                      41     
                      42     ;   <o.5..7> CPU Clock Rate for X'tal 12 MHz  <0x00=> Fhosc/128 <0x01=> Fhosc/64 <0x02=> Fh
                             osc/32 <0x03=> Fhosc/16 <0x04=> Fhosc/8 <0x05=> Fhosc/4  <0x06=> Fhosc/2
  00C0                43         XTAL12M_CLOCKRATE_SET    EQU     0xC0               ;       {0x7FFB}
                      44     ;   <i> FCPU for X'tal 12 MHz is Fhosc/2~Fhosc/128.
                      45     
                      46     ;   <o.5..7> CPU Clock Rate for X'tal 4 MHz  <0x00=> Fhosc/128 <0x01=> Fhosc/64 <0x02=> Fho
                             sc/32 <0x03=> Fhosc/16 <0x04=> Fhosc/8 <0x05=> Fhosc/4  <0x06=> Fhosc/2 <0x07=> Fhosc/1 
  00E0                47         XTAL4M_CLOCKRATE_SET    EQU     0xE0                ;       {0x7FFB}
                      48     ;   <i> FCPU for X'tal 4 MHz is Fhosc/1~Fhosc/128.
                      49     
                      50     ;   <o.5..7> CPU Clock Rate for External Clock  <0x00=> Fhosc/128 <0x01=> Fhosc/64 <0x02=> 
                             Fhosc/32 <0x03=> Fhosc/16 <0x04=> Fhosc/8 <0x05=> Fhosc/4  <0x06=> Fhosc/2 <0x07=> Fhosc/1 
A51 MACRO ASSEMBLER  OPTIONS_SN8F5835                                                     04/27/2022 11:38:43 PAGE     2

  00C0                51         EXTERNAL_CLOCKRATE_SET    EQU     0xC0              ;       {0x7FFB}
                      52     ;   <i> FCPU for External Clock is Fhosc/1~Fhosc/128.
                      53     
                      54     ;   </h>
                      55     
                      56     ;   <o.0> Noise Filter <0x01=> Disable <0x00=> Enable
  0001                57         NOISEFILT_SET   EQU     0x01                ;       {0x7FFC}
                      58             
                      59     ;       <o.3> CK_Fine_Tuning <0x01=> Disable <0x00=> Enable
  0008                60         CK_Fine_Tuning_SET   EQU     0x08           ;       {0x7FFF}
                      61     ;   <i> IHRC frequency fine tuning function.
                      62     
                      63     ;
                      64     ;   <h> Reset Sources
                      65     ;
                      66     ;       <o.4..5> External Reset / GPIO Shared Pin <0x00=> Reset with De-bounce <0x02=> Rese
                             t without De-bounce <0x03=> GPIO
  0030                67             RESETPIN_SET    EQU     0x30    ;       {0x7FFC}
                      68     ;       <i> Reset with De-bounce: Triggers reset if this pin is pulled low over 8 ms.
                      69     ;       <i> Reset without De-bounce: Triggers reset immediately if this pin is pulled low.
                      70     ;       <i> GPIO: The shared pin is reserved for general purpose input/output.
                      71     ;       <i> The de-bounce period is based on Internal Low R-C Clock which has a gentle inac
                             curacy.
                      72     ;
                      73     ;       <o.4..7> Watchdog Reset <0x00=> Always <0x05=> Enable <0x0A=> Disable 
  00A0                74             WATCHDOG_SET    EQU     0xA0    ;       {0x7FFF}
                      75     ;       <i> Always: Trun on watchdog function including Normal, IDLE, and STOP mode.
                      76     ;       <i> Enable: Turn on watchdog function only in Normal mode.
                      77     ;       <i> Disable: Turn off watchdog function.
                      78     ;
                      79     ;       <o.6..7> Watchdog Overflow Period <0x00=> 64 ms <0x01=> 128 ms <0x02=> 256 ms <0x03
                             => 512 ms
  00C0                80             WATCHCLK_SET    EQU     0xC0    ;       {0x7FFC}
                      81     ;       <i> The watchdog overflow period is based on Internal Low R-C Clock which has a gen
                             tle inaccuracy.
                      82     ;   </h>
                      83     
                      84     
                      85     ;------------------------------------------------------------------------------
                      86     ;       CRC region define
                      87     ;------------------------------------------------------------------------------ 
                      88     ;  <h> CRC verify
                      89     ;    <o> 16BIT_BYPASS1P_H <0x00-0xFF>
                      90     ;      <i> High byte of 16BIT CRC that bypass last 1page+2byte (range: 0x00 - 0xFF)
  00EA                91     BIT16_BYPASS1P_H                EQU             0xEA
                      92     ;    <o> 16BIT_BYPASS1P_L <0x00-0xFF>
                      93     ;      <i> Low byte of CRC that bypass last 1page+2byte (range: 0x00 - 0xFF)
  0001                94     BIT16_BYPASS1P_L                EQU             0x01
                      95     
                      96     
                      97                     PUBLIC  CRC_CHECK_DATA
                      98     
----                  99         CSEG    AT      0x7FF0
7FF0                 100     CRC_CHECK_DATA:
7FF0 EA              101                     DB                      BIT16_BYPASS1P_H
7FF1 01              102                     DB                      BIT16_BYPASS1P_L        
                     103                             
                     104                             
----                 105         CSEG    AT      0x7FF6
7FF6 FF              106         DB      0xFF
7FF7 FF              107         DB      0xFF
7FF8 FF              108         DB      0xFF
7FF9 FF              109         DB      0xFF
7FFA FF              110         DB      0xFF
                     111             IF              CLOCKSRC_SET==0x18
7FFB BF              112         DB      IHRC32M_CLOCKRATE_SET + CLOCKSRC_SET + 0x06 + 0x01
A51 MACRO ASSEMBLER  OPTIONS_SN8F5835                                                     04/27/2022 11:38:43 PAGE     3

                     113             ENDIF
                     114             IF              CLOCKSRC_SET==0x08
                                 DB      XTAL12M_CLOCKRATE_SET + CLOCKSRC_SET + 0x06 + 0x01
                                     ENDIF
                     117             IF              CLOCKSRC_SET==0x00
                                 DB      XTAL4M_CLOCKRATE_SET + CLOCKSRC_SET + 0x06 + 0x01
                                     ENDIF
                     120             IF              CLOCKSRC_SET==0x10
                                 DB      EXTERNAL_CLOCKRATE_SET + CLOCKSRC_SET + 0x06 + 0x01
                                     ENDIF
7FFC FF              123         DB      WATCHCLK_SET +  RESETPIN_SET + 0x08 + 0x06 + NOISEFILT_SET
7FFD 5A              124         DB          0x5A
7FFE A5              125         DB          0xA5
7FFF AF              126         DB      WATCHDOG_SET + CK_Fine_Tuning_SET + ISP_EN_SET + SECURITY_SET
                     127         END
A51 MACRO ASSEMBLER  OPTIONS_SN8F5835                                                     04/27/2022 11:38:43 PAGE     4

SYMBOL TABLE LISTING
------ ----- -------


N A M E                 T Y P E  V A L U E   ATTRIBUTES

BIT16_BYPASS1P_H . . .  N NUMB   00EAH   A   
BIT16_BYPASS1P_L . . .  N NUMB   0001H   A   
CK_FINE_TUNING_SET . .  N NUMB   0008H   A   
CLOCKSRC_SET . . . . .  N NUMB   0018H   A   
CRC_CHECK_DATA . . . .  C ADDR   7FF0H   A   
EXTERNAL_CLOCKRATE_SET  N NUMB   00C0H   A   
IHRC32M_CLOCKRATE_SET.  N NUMB   00A0H   A   
ISP_EN_SET . . . . . .  N NUMB   0004H   A   
NOISEFILT_SET. . . . .  N NUMB   0001H   A   
RESETPIN_SET . . . . .  N NUMB   0030H   A   
ROM_SIZE . . . . . . .  N NUMB   8000H   A   
SECURITY_SET . . . . .  N NUMB   0003H   A   
WATCHCLK_SET . . . . .  N NUMB   00C0H   A   
WATCHDOG_SET . . . . .  N NUMB   00A0H   A   
XTAL12M_CLOCKRATE_SET.  N NUMB   00C0H   A   
XTAL4M_CLOCKRATE_SET .  N NUMB   00E0H   A   


REGISTER BANK(S) USED: 0 


ASSEMBLY COMPLETE.  0 WARNING(S), 0 ERROR(S)
