C51 COMPILER V9.54   MAIN                                                                  04/27/2022 11:38:43 PAGE 1   


C51 COMPILER V9.54, COMPILATION OF MODULE MAIN
OBJECT MODULE PLACED IN .\Objects\main.obj
COMPILER INVOKED BY: C:\Keil_v5\C51\BIN\C51.EXE source\main.c OPTIMIZE(8,SPEED) BROWSE DEBUG OBJECTEXTEND PRINT(.\Listin
                    -gs\main.lst) TABS(2) OBJECT(.\Objects\main.obj)

line level    source

   1          /******************** (C) COPYRIGHT 2021 SONiX *******************************
   2          * COMPANY:  SONiX
   3          * DATE:   2021/12/27
   4          * IC:     SN8F5754
   5          *____________________________________________________________________________
   6          * REVISION    Date        Author    Description
   7          * 1.0         2021/12/27  SONiX     1. First release
   8          *____________________________________________________________________________
   9          *****************************************************************************/
  10          /*_____ I N C L U D E S _________________________________*/
  11          #define __XRAM_SFR_H__
  12          #include <SN8F5835.h>
  13          #include "crc.h"
  14          
  15          /*_____ F U N C T I O N S _______________________________*/
  16          void GPIO_Initialization(void);
  17          
  18          /*_____ D E F I N I T I O N S ___________________________*/
  19          #define ROM_SIZE                    0x4000
  20          #define PAGE_SIZE                   0x20
  21          /*_____ D E C L A R A T I O N S _________________________*/
  22          extern uint16_t code CRC_CHECK_DATA;
  23          
  24          /*_____ M A C R O S _____________________________________*/
  25          #define    IO_PORT0_OUTPUT_LOW        P0M |= 0xFF;    P0 &= 0x00;
  26          #define    IO_PORT1_OUTPUT_LOW        P1M |= 0xFF;    P1 &= 0x00;
  27          #define    IO_PORT3_OUTPUT_LOW        P3M |= 0xFF;    P3 &= 0x00;
  28          #define    IO_PORT4_OUTPUT_LOW        P4M |= 0xFF;    P4 &= 0x00;
  29          
  30          #define OB_IO_OUTPUT_LOW      P00=0;  P0M |=0x01; 
  31          #define OB_IO_OUTPUT_HIGH     P00=1;  P0M |=0x01;
  32          
  33          
  34          /**
  35           *  @Brief    main: CRC Test Demo Function
  36           *  @param    None
  37           *  @retval   None
  38           */
  39          
  40          void main(void)
  41          {
  42   1       uint16_t dbCRC16_OneByte_Result;
  43   1        uint16_t dbCRC16_AppResult;
  44   1        uint16_t dbCRC16_RANGE_ADDR = (ROM_SIZE - PAGE_SIZE - 0x02);
  45   1        uint16_t i;
  46   1        uint8_t code *Addrptr;
  47   1        uint8_t code *AddrprtCRCOption;
  48   1        
  49   1        /*  Initialize GPIO status  */
  50   1        GPIO_Initialization();
  51   1        
  52   1        /*  Initialize and Configurate CRC data */
  53   1        Addrptr = 0x0000;
  54   1        AddrprtCRCOption = (uint8_t code *)&CRC_CHECK_DATA;
C51 COMPILER V9.54   MAIN                                                                  04/27/2022 11:38:43 PAGE 2   

  55   1        
  56   1        while(1)
  57   1        {
  58   2          /*  For example, one byte calculate with CRC CRC16-CCITT */
  59   2          /*  (1) CRC mode configuration 
  60   2              (2) CRC seed initialization */
  61   2          CRCM = mskCRCM_CRC16 | mskCRCM_RANGE_BYPASS1 | mskCRCM_ENABLE;    /* (1)  */
  62   2          CRCM |= mskCRCM_RESET;                                            /* (2)  */
  63   2          
  64   2          /* Accumulate ROM to last 1page and 2byte by using for loop one byte CRC calculation */
  65   2          for (i = 0x0; i < dbCRC16_RANGE_ADDR; i+= 0x1)
  66   2          {
  67   3            CRCDATL = *(Addrptr + i);
  68   3            while ((CRCM & mskCRCM_BUSY) != 0x00);
  69   3            dbCRC16_OneByte_Result = (CRCDATH << 8) | CRCDATL;  
  70   3          }
  71   2          /*  Compare wtih HW result and App result, the APP results were be set on OPTIONS_SN8F5754.A51  */
  72   2          dbCRC16_AppResult = (*(AddrprtCRCOption+0)<<8) + *(AddrprtCRCOption+1);   
  73   2          
  74   2          /*  If HW CRC result is right, IO output high
  75   2              If HW CRC result is wrong, IO output low  */
  76   2          if(dbCRC16_OneByte_Result==dbCRC16_AppResult)
  77   2          {
  78   3            OB_IO_OUTPUT_HIGH
  79   3          }
  80   2          else
  81   2          {
  82   3            OB_IO_OUTPUT_LOW
  83   3          } 
  84   2        }
  85   1      }
  86          
  87          
  88          /**
  89           *  @Brief    Initialize GPIO status
  90           *  @param    None
  91           *  @retval   None
  92           */
  93          void GPIO_Initialization(void)
  94          {
  95   1        /*  Set whole IOs to output low */
  96   1          IO_PORT0_OUTPUT_LOW
  97   1          IO_PORT1_OUTPUT_LOW
  98   1          IO_PORT3_OUTPUT_LOW
  99   1          IO_PORT4_OUTPUT_LOW    
 100   1      }
 101          


MODULE INFORMATION:   STATIC OVERLAYABLE
   CODE SIZE        =    144    ----
   CONSTANT SIZE    =   ----    ----
   XDATA SIZE       =   ----    ----
   PDATA SIZE       =   ----    ----
   DATA SIZE        =   ----       8
   IDATA SIZE       =   ----    ----
   BIT SIZE         =   ----    ----
END OF MODULE INFORMATION.


C51 COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)
