C51 COMPILER V9.54   SPI                                                                   05/31/2022 16:56:54 PAGE 1   


C51 COMPILER V9.54, COMPILATION OF MODULE SPI
OBJECT MODULE PLACED IN .\Objects\SPI.obj
COMPILER INVOKED BY: C:\Keil_v5\C51\BIN\C51.EXE source\SPI.c OPTIMIZE(8,SPEED) BROWSE DEBUG OBJECTEXTEND PRINT(.\Listing
                    -s\SPI.lst) TABS(2) OBJECT(.\Objects\SPI.obj)

line level    source

   1          /*_____ I N C L U D E S _________________________________*/
   2          #include "SPI.h"
   3          
   4          /*_____ F U N C T I O N S _______________________________*/
   5          
   6          /*_____ D E F I N I T I O N S ___________________________*/
   7          
   8          /*_____ D E C L A R A T I O N S _________________________*/
   9          uint8_t bTX_complete=0,bRX_complete=0;
  10          uint8_t bTX_buffer=0,bRX_buffer=0;
  11          uint8_t bRX_count=0x00;
  12          uint8_t clk,type;
  13          
  14          /*_____ M A C R O S _____________________________________*/
  15          
  16          
  17          /**
  18           * @brief This function will initialize the SPI.
  19           * @param clk_select: \n
  20           *        \t 0x00 : SPI_RATE_FCPUDIV2 (4 MHz) \n
  21           *        \t 0x01 : SPI_RATE_FCPUDIV4 (2 MHz) \n
  22           *        \t 0x02 : SPI_RATE_FCPUDIV8 (1 MHz) \n
  23           *        \t 0x03 : SPI_RATE_FCPUDIV16 (500 KMHz) \n
  24           *        \t 0x80 : SPI_RATE_FCPUDIV32 (250 KHz) \n
  25           *        \t 0x81 : SPI_RATE_FCPUDIV64 (125 KHz) \n
  26           *        \t 0x82 : SPI_RATE_FCPUDIV128 (62.5 KHz) \n
  27           * @param type_select: Clock phase for edge sampling and clock polarity selection setting.
  28           *              \t SPI_Type0 : CPHA = 0, CPOL = 0 \n
  29           *              \t SPI_Type1 : CPHA = 0, CPOL = 1 \n
  30           *              \t SPI_Type2 : CPHA = 1, CPOL = 0 \n
  31           *              \t SPI_Type3 : CPHA = 1, CPOL = 1
  32           * @param SPI_EN: Base on Master setting
  33           *              \t spi_interrupt  0x00  interrupt disable \n
  34           *              \t spi_interrupt  0x01  interrupt enable  \n
  35           * @return None
  36           */
  37          void SPI_init(clk,type,spi_interrupt,spi_init_data)
  38          {
  39   1        //SSN &SCK & MOSI =INPUT , MISO=OUTPUT;
  40   1        P0M &=0x8F;   
  41   1        clk_select(clk);
  42   1        type_select(type);
  43   1        
  44   1        SPI_EN(spi_interrupt);
  45   1        SPDAT=spi_init_data;
  46   1      }
  47          void clk_select(uint8_t clk_cmd)
  48          {
  49   1        switch(clk_cmd)
  50   1        {
  51   2          case 0x00:
  52   2            clk=mskSPCON_SPR_DIV2;  // Fcpu/2
  53   2            break;
  54   2          case 0x01:
C51 COMPILER V9.54   SPI                                                                   05/31/2022 16:56:54 PAGE 2   

  55   2            clk=mskSPCON_SPR_DIV4;  // Fcpu/4
  56   2            break;
  57   2          case 0x02:
  58   2            clk=mskSPCON_SPR_DIV8;  // Fcpu/8
  59   2            break;
  60   2          case 0x03:
  61   2            clk=mskSPCON_SPR_DIV16; // Fcpu/16
  62   2            break;
  63   2          case 0x04:
  64   2            clk=mskSPCON_SPR_DIV32; // Fcpu/32
  65   2            break;
  66   2          case 0x05:
  67   2            clk=mskSPCON_SPR_DIV64; // Fcpu/64
  68   2            break;
  69   2          case 0x06:
  70   2            clk=mskSPCON_SPR_DIV128;  // Fcpu/128
  71   2            break;  
  72   2        }
  73   1      }
  74          void type_select(uint8_t type_cmd)
  75          {
  76   1        switch(type_cmd)
  77   1        {
  78   2          case 0x00:
  79   2            type=mskSPCON_MODE1;  // SPI_Type0 : CPOL = 0, CPHA = 0 
  80   2            break;
  81   2          case 0x01:
  82   2            type=mskSPCON_MODE2;  // SPI_Type1 : CPOL = 0, CPHA = 1
  83   2            break;
  84   2          case 0x02:
  85   2            type=mskSPCON_MODE3;  // SPI_Type2 : CPOL = 1, CPHA = 0
  86   2            break;
  87   2          case 0x03:
  88   2            type=mskSPCON_MODE4;  // SPI_Type3 : CPOL = 1, CPHA = 1 
  89   2            break;
  90   2        }
  91   1      }
  92          void SPI_EN(uint8_t interrupt_cmd)
  93          {
  94   1          //P04=SSN,P05=SCK,P06=MOSI,P07=MISO  
  95   1          //SPI Enalbe ,SPI MASTER MODE,SSDIS DISABLE
  96   1          SPCON &=0x00;
  97   1          SPCON &= ~(mskSPCON_MASTER);  // Slave Mode
  98   1          SPCON |= clk|type;
  99   1          //SPCON |=mskSPCON_SSDIS; 
 100   1          SPCON |= mskSPCON_SPEN;   // SPI ENALBE
 101   1          switch(interrupt_cmd)
 102   1          {
 103   2            case 0x00:
 104   2              ESPI=0; //SPI interrupt disalbe
 105   2              EAL=0;  // global interrupt disalbe
 106   2              break;
 107   2            case 0x01:
 108   2              ESPI=1; //SPI interrupt enalbe
 109   2              EAL=1;  // global interrupt enalbe
 110   2              break;
 111   2          }
 112   1      }
 113          
 114          uint8_t SPI_rx(uint8_t bSend_data,uint8_t bLength)
 115          {
 116   1        
C51 COMPILER V9.54   SPI                                                                   05/31/2022 16:56:54 PAGE 3   

 117   1        while((SPSTA&&SPIF)==0);    //wait SPI recevice over
 118   1        bRX_buffer=SPDAT;
 119   1          
 120   1        SPDAT=bSend_data;
 121   1        bRX_count++;
 122   1        if(bRX_count>=bLength)
 123   1        {
 124   2          bRX_count=0;
 125   2        }
 126   1        return bRX_buffer;
 127   1      }
 128          


MODULE INFORMATION:   STATIC OVERLAYABLE
   CODE SIZE        =    187    ----
   CONSTANT SIZE    =   ----    ----
   XDATA SIZE       =   ----    ----
   PDATA SIZE       =   ----    ----
   DATA SIZE        =      7       8
   IDATA SIZE       =   ----    ----
   BIT SIZE         =   ----    ----
END OF MODULE INFORMATION.


C51 COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)
