$NOMOD51
;------------------------------------------------------------------------------
;
;  Copyright (c) 2019 SONiX Technology Co., Ltd.
;  Version 1.0 - SN8F5835, SN8F5834, SN8F5833. Add code option address for MP5
;  Version 1.1 - Modify CPU Clock Rate option.
;  Version 1.2 - Add CRC region define.
;  *** <<< Use Configuration Wizard in Context Menu >>> ***
;------------------------------------------------------------------------------
;
;  This preference, such as watchdog, external reset pin, and clock source, is preloaded 
;  during the microcontroller's power-on. It is strongly recommanded to use configuration 
;  wizard to set these parameters up appropriately.
;
;------------------------------------------------------------------------------
ROM_SIZE		EQU		0x8000
;
;	<o.0..1> Program Memory Security <0x03=> Security Disable <0x02=> Security Enable <0x00=> Security Configuration
	SECURITY_SET    EQU     0x03		;	{0x7FFF}
;   <i> Security Disable: all address ROM data can be accessed.	
;   <i> Security Enable: all address ROM data are protected.
;   <i> Security Configuration: all address ROM data are protected expect address 0x7E00 ~ 0x7FBF ROM data can be accessed.
;
;   <o.2> ISP Program Area  <0x01=> All Page <0x00=> Page 504~ Page 510
    ISP_EN_SET    EQU     0x04		;	{0x7FFF}
;   <i> All Page: all address can perform ISP function.
;   <i> Page 504 ~ Page 510: only address 0x7E00 ~ 0x7FBF can perform ISP function.

;   <h> CPU Clock

;   <o.3..4> CPU Clock Source <0x03=> IHRC 32 MHz <0x01=> X'tal 12 MHz <0x00=> X'tal 4 MHz <0x02=> External Clock
    CLOCKSRC_SET    EQU     0x18		;	{0x7FFB}
;   <i> IHRC 32 MHz: on-chip internal clock.
;   <i> X'tal 12 MHz: off-chip crystal between 8 MHz and 16 MHz.
;   <i> X'tal 4 MHz: off-chip crystal between 1 MHz and 8 MHz.
;   <i> External Clock: external clock input from XIN pin.

;   <o.5..7> CPU Clock Rate for IHRC 32MHz  <0x00=> Fhosc/128 <0x01=> Fhosc/64 <0x02=> Fhosc/32 <0x03=> Fhosc/16 <0x04=> Fhosc/8 <0x05=> Fhosc/4
    IHRC32M_CLOCKRATE_SET    EQU     0xA0		;	{0x7FFB}
;   <i> FCPU for IHRC 32MHz is Fhosc/4~Fhosc/128.

;   <o.5..7> CPU Clock Rate for X'tal 12 MHz  <0x00=> Fhosc/128 <0x01=> Fhosc/64 <0x02=> Fhosc/32 <0x03=> Fhosc/16 <0x04=> Fhosc/8 <0x05=> Fhosc/4  <0x06=> Fhosc/2
    XTAL12M_CLOCKRATE_SET    EQU     0xC0		;	{0x7FFB}
;   <i> FCPU for X'tal 12 MHz is Fhosc/2~Fhosc/128.

;   <o.5..7> CPU Clock Rate for X'tal 4 MHz  <0x00=> Fhosc/128 <0x01=> Fhosc/64 <0x02=> Fhosc/32 <0x03=> Fhosc/16 <0x04=> Fhosc/8 <0x05=> Fhosc/4  <0x06=> Fhosc/2 <0x07=> Fhosc/1 
    XTAL4M_CLOCKRATE_SET    EQU     0xE0		;	{0x7FFB}
;   <i> FCPU for X'tal 4 MHz is Fhosc/1~Fhosc/128.

;   <o.5..7> CPU Clock Rate for External Clock  <0x00=> Fhosc/128 <0x01=> Fhosc/64 <0x02=> Fhosc/32 <0x03=> Fhosc/16 <0x04=> Fhosc/8 <0x05=> Fhosc/4  <0x06=> Fhosc/2 <0x07=> Fhosc/1 
    EXTERNAL_CLOCKRATE_SET    EQU     0xC0		;	{0x7FFB}
;   <i> FCPU for External Clock is Fhosc/1~Fhosc/128.

;   </h>

;   <o.0> Noise Filter <0x01=> Disable <0x00=> Enable
    NOISEFILT_SET   EQU     0x01		;	{0x7FFC}
	
;	<o.3> CK_Fine_Tuning <0x01=> Disable <0x00=> Enable
    CK_Fine_Tuning_SET   EQU     0x08		;	{0x7FFF}
;   <i> IHRC frequency fine tuning function.

;
;   <h> Reset Sources
;
;       <o.4..5> External Reset / GPIO Shared Pin <0x00=> Reset with De-bounce <0x02=> Reset without De-bounce <0x03=> GPIO
        RESETPIN_SET    EQU     0x30	;	{0x7FFC}
;       <i> Reset with De-bounce: Triggers reset if this pin is pulled low over 8 ms.
;       <i> Reset without De-bounce: Triggers reset immediately if this pin is pulled low.
;       <i> GPIO: The shared pin is reserved for general purpose input/output.
;       <i> The de-bounce period is based on Internal Low R-C Clock which has a gentle inaccuracy.
;
;       <o.4..7> Watchdog Reset <0x00=> Always <0x05=> Enable <0x0A=> Disable 
        WATCHDOG_SET    EQU     0xA0	;	{0x7FFF}
;       <i> Always: Trun on watchdog function including Normal, IDLE, and STOP mode.
;       <i> Enable: Turn on watchdog function only in Normal mode.
;       <i> Disable: Turn off watchdog function.
;
;       <o.6..7> Watchdog Overflow Period <0x00=> 64 ms <0x01=> 128 ms <0x02=> 256 ms <0x03=> 512 ms
        WATCHCLK_SET    EQU     0xC0	;	{0x7FFC}
;       <i> The watchdog overflow period is based on Internal Low R-C Clock which has a gentle inaccuracy.
;   </h>


;------------------------------------------------------------------------------
;	CRC region define
;------------------------------------------------------------------------------	
;  <h> CRC verify
;    <o> 16BIT_BYPASS1P_H <0x00-0xFF>
;      <i> High byte of 16BIT CRC that bypass last 1page+2byte (range: 0x00 - 0xFF)
BIT16_BYPASS1P_H		EQU		0x1E
;    <o> 16BIT_BYPASS1P_L <0x00-0xFF>
;      <i> Low byte of CRC that bypass last 1page+2byte (range: 0x00 - 0xFF)
BIT16_BYPASS1P_L		EQU		0xAF


		PUBLIC	CRC_CHECK_DATA

    CSEG    AT      0x7FF0
CRC_CHECK_DATA:
		DB			BIT16_BYPASS1P_H
		DB			BIT16_BYPASS1P_L	
			
			
    CSEG    AT      0x7FF6
    DB      0xFF
    DB      0xFF
    DB      0xFF
    DB      0xFF
    DB      0xFF
	IF		CLOCKSRC_SET==0x18
    DB      IHRC32M_CLOCKRATE_SET + CLOCKSRC_SET + 0x06 + 0x01
	ENDIF
	IF		CLOCKSRC_SET==0x08
    DB      XTAL12M_CLOCKRATE_SET + CLOCKSRC_SET + 0x06 + 0x01
	ENDIF
	IF		CLOCKSRC_SET==0x00
    DB      XTAL4M_CLOCKRATE_SET + CLOCKSRC_SET + 0x06 + 0x01
	ENDIF
	IF		CLOCKSRC_SET==0x10
    DB      EXTERNAL_CLOCKRATE_SET + CLOCKSRC_SET + 0x06 + 0x01
	ENDIF
    DB      WATCHCLK_SET +  RESETPIN_SET + 0x08 + 0x06 + NOISEFILT_SET
    DB		0x5A
    DB		0xA5
    DB      WATCHDOG_SET + CK_Fine_Tuning_SET + ISP_EN_SET + SECURITY_SET
    END
